Update capstone
authorysuzuki@apple.com <ysuzuki@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Fri, 25 Dec 2020 10:35:21 +0000 (10:35 +0000)
committerysuzuki@apple.com <ysuzuki@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Fri, 25 Dec 2020 10:35:21 +0000 (10:35 +0000)
https://bugs.webkit.org/show_bug.cgi?id=219941

Reviewed by Michael Catanzaro.

* capstone/CMakeLists.txt:
* capstone/Source/.gitignore:
* capstone/Source/.travis.yml:
* capstone/Source/CMakeLists.txt:
* capstone/Source/COMPILE.TXT:
* capstone/Source/COMPILE_CMAKE.TXT:
* capstone/Source/COMPILE_MSVC.TXT:
* capstone/Source/CREDITS.TXT:
* capstone/Source/ChangeLog-capstone:
* capstone/Source/HACK.TXT:
* capstone/Source/LEB128.h:
(decodeULEB128):
* capstone/Source/MCDisassembler.h:
* capstone/Source/MCFixedLenDisassembler.h:
* capstone/Source/MCInst.c:
(MCInst_Init):
(MCInst_clear):
(MCInst_insert0):
(MCInst_setOpcode):
(MCInst_setOpcodePub):
(MCInst_getOpcode):
(MCInst_getOpcodePub):
(MCInst_getOperand):
(MCInst_getNumOperands):
(MCInst_addOperand2):
(MCOperand_isValid):
(MCOperand_isReg):
(MCOperand_isImm):
(MCOperand_isFPImm):
(MCOperand_getReg):
(MCOperand_setReg):
(MCOperand_getImm):
(MCOperand_setImm):
(MCOperand_getFPImm):
(MCOperand_setFPImm):
(MCOperand_CreateReg1):
(MCOperand_CreateReg0):
(MCOperand_CreateImm1):
(MCOperand_CreateImm0):
(MCOperand_Init): Deleted.
* capstone/Source/MCInst.h:
* capstone/Source/MCInstrDesc.c:
(MCOperandInfo_isPredicate):
(MCOperandInfo_isOptionalDef):
* capstone/Source/MCInstrDesc.h:
* capstone/Source/MCRegisterInfo.c:
(MCRegisterInfo_InitMCRegisterInfo):
(DiffListIterator_init):
(DiffListIterator_getVal):
(DiffListIterator_next):
(DiffListIterator_isValid):
(MCRegisterInfo_getMatchingSuperReg):
(MCRegisterInfo_getSubReg):
(MCRegisterInfo_getRegClass):
(MCRegisterClass_contains):
* capstone/Source/MCRegisterInfo.h:
* capstone/Source/Makefile:
* capstone/Source/MathExtras.h:
(Hi_32):
(Lo_32):
(isUIntN):
(isMask_32):
(isMask_64):
(isShiftedMask_32):
(isShiftedMask_64):
(isPowerOf2_32):
(CountLeadingZeros_32):
(CountLeadingOnes_32):
(CountLeadingZeros_64):
(CountLeadingOnes_64):
(CountTrailingZeros_32):
(CountTrailingOnes_32):
(CountTrailingZeros_64):
(CountTrailingOnes_64):
(CountPopulation_32):
(CountPopulation_64):
(Log2_32):
(Log2_64):
(Log2_32_Ceil):
(Log2_64_Ceil):
(GreatestCommonDivisor64):
(BitsToDouble):
(BitsToFloat):
(DoubleToBits):
(FloatToBits):
(MinAlign):
(NextPowerOf2):
(RoundUpToAlignment):
(OffsetToAlignment):
(abs64):
(SignExtend32):
(SignExtend64):
(countLeadingZeros):
* capstone/Source/README.md:
* capstone/Source/SPONSORS.TXT: Added.
* capstone/Source/SStream.c:
(SStream_Init):
(SStream_concat0):
(SStream_concat):
(printInt64Bang):
(printUInt64Bang):
(printInt64):
(printInt32BangDec):
(printInt32Bang):
(printInt32):
(printUInt32Bang):
(printUInt32):
* capstone/Source/SStream.h:
* capstone/Source/arch/ARM/ARMAddressingModes.h:
(ARM_AM_getAddrOpcStr):
(ARM_AM_getShiftOpcStr):
(ARM_AM_getShiftOpcEncoding):
(ARM_AM_getAMSubModeStr):
(rotr32):
(rotl32):
(getSORegOpc):
(getSORegOffset):
(ARM_AM_getSORegShOp):
(getSOImmValImm):
(getSOImmValRot):
(getSOImmValRotate):
(getSOImmVal):
(isSOImmTwoPartVal):
(getSOImmTwoPartFirst):
(getSOImmTwoPartSecond):
(getThumbImmValShift):
(isThumbImmShiftedVal):
(getThumbImm16ValShift):
(isThumbImm16ShiftedVal):
(getThumbImmNonShiftedVal):
(getT2SOImmValSplatVal):
(getT2SOImmValRotateVal):
(getT2SOImmVal):
(getT2SOImmValRotate):
(isT2SOImmTwoPartVal):
(getT2SOImmTwoPartFirst):
(getT2SOImmTwoPartSecond):
(ARM_AM_getAM2Opc):
(getAM2Offset):
(getAM2Op):
(getAM2ShiftOpc):
(getAM2IdxMode):
(getAM3Opc):
(getAM3Offset):
(getAM3Op):
(getAM3IdxMode):
(getAM4SubMode):
(getAM4ModeImm):
(ARM_AM_getAM5Opc):
(ARM_AM_getAM5Offset):
(ARM_AM_getAM5Op):
(createNEONModImm):
(getNEONModImmOpCmode):
(getNEONModImmVal):
(ARM_AM_decodeNEONModImm):
(getFPImmFloat):
* capstone/Source/arch/ARM/ARMBaseInfo.h:
(ARMCC_getOppositeCondition):
(ARMCC_ARMCondCodeToString):
(ARM_PROC_IFlagsToString):
(ARM_PROC_IModToString):
(ARM_MB_MemBOptToString):
(ARM_ISB_InstSyncBOptToString):
(isARMLowRegister):
(ARMII_AddrModeToString):
* capstone/Source/arch/ARM/ARMDisassembler.c:
(ITStatus_push_back):
(ITStatus_instrInITBlock):
(ITStatus_instrLastInITBlock):
(ITStatus_getITCC):
(ITStatus_advanceITState):
(ITStatus_setITState):
(Check):
(ARM_getFeatureBits):
(DecodePredicateOperand):
(ARM_init):
(checkDecodedInstruction):
(_ARM_getInstruction):
(AddThumb1SBit):
(AddThumbPredicate):
(UpdateThumbVFPPredicate):
(_Thumb_getInstruction):
(Thumb_getInstruction):
(ARM_getInstruction):
(DecodeGPRnopcRegisterClass):
(DecodeGPRwithAPSRRegisterClass):
(DecodetGPRRegisterClass):
(DecodetcGPRRegisterClass):
(DecoderGPRRegisterClass):
(DecodeDPRRegisterClass):
(DecodeDPR_8RegisterClass):
(DecodeDPR_VFP2RegisterClass):
(DecodeDPairRegisterClass):
(DecodeCCOutOperand):
(DecodeSORegImmOperand):
(DecodeSORegRegOperand):
(DecodeRegListOperand):
(DecodeSPRRegListOperand):
(DecodeDPRRegListOperand):
(DecodeBitfieldMaskOperand):
(DecodeCopMemInstruction):
(DecodeAddrMode2IdxInstruction):
(DecodeSORegMemOperand):
(DecodeAddrMode3Instruction):
(DecodeRFEInstruction):
(DecodeQADDInstruction):
(DecodeMemMultipleWritebackInstruction):
(DecodeCPSInstruction):
(DecodeT2CPSInstruction):
(DecodeT2MOVTWInstruction):
(DecodeArmMOVTWInstruction):
(DecodeSMLAInstruction):
(DecodeAddrModeImm12Operand):
(DecodeAddrMode5Operand):
(DecodeAddrMode7Operand):
(DecodeT2BInstruction):
(DecodeBranchImmInstruction):
(DecodeAddrMode6Operand):
(DecodeVLDInstruction):
(DecodeVLDST1Instruction):
(DecodeVLDST2Instruction):
(DecodeVLDST3Instruction):
(DecodeVLDST4Instruction):
(DecodeVSTInstruction):
(DecodeVLD1DupInstruction):
(DecodeVLD2DupInstruction):
(DecodeVLD3DupInstruction):
(DecodeVLD4DupInstruction):
(DecodeNEONModImmInstruction):
(DecodeVSHLMaxInstruction):
(DecodeShiftRight8Imm):
(DecodeShiftRight16Imm):
(DecodeShiftRight32Imm):
(DecodeShiftRight64Imm):
(DecodeTBLInstruction):
(DecodeThumbAddSpecialReg):
(DecodeThumbBROperand):
(DecodeT2BROperand):
(DecodeThumbCmpBROperand):
(DecodeThumbAddrModeRR):
(DecodeThumbAddrModeIS):
(DecodeThumbAddrModePC):
(DecodeThumbAddrModeSP):
(DecodeT2AddrModeSOReg):
(DecodeT2LoadShift):
(DecodeT2LoadImm8):
(DecodeT2LoadImm12):
(DecodeT2LoadT):
(DecodeT2LoadLabel):
(DecodeT2Imm8S4):
(DecodeT2AddrModeImm8s4):
(DecodeT2AddrModeImm0_1020s4):
(DecodeT2Imm8):
(DecodeT2AddrModeImm8):
(DecodeT2LdStPre):
(DecodeT2AddrModeImm12):
(DecodeThumbAddSPImm):
(DecodeThumbAddSPReg):
(DecodeThumbCPS):
(DecodePostIdxReg):
(DecodeThumbBLXOffset):
(DecodeCoprocessor):
(DecodeThumbTableBranch):
(DecodeThumb2BCCInstruction):
(DecodeT2SOImm):
(DecodeThumbBCCTargetOperand):
(DecodeThumbBLTargetOperand):
(DecodeMemBarrierOption):
(DecodeInstSyncBarrierOption):
(DecodeMSRMask):
(DecodeBankedReg):
(DecodeDoubleRegLoad):
(DecodeDoubleRegStore):
(DecodeLDRPreImm):
(DecodeLDRPreReg):
(DecodeSTRPreImm):
(DecodeSTRPreReg):
(DecodeVLD1LN):
(DecodeVST1LN):
(DecodeVLD2LN):
(DecodeVST2LN):
(DecodeVLD3LN):
(DecodeVST3LN):
(DecodeVLD4LN):
(DecodeVST4LN):
(DecodeVMOVSRR):
(DecodeVMOVRRS):
(DecodeIT):
(DecodeT2LDRDPreInstruction):
(DecodeT2STRDPreInstruction):
(DecodeT2Adr):
(DecodeT2ShifterImmOperand):
(DecodeSwap):
(DecodeVCVTD):
(DecodeVCVTQ):
(DecodeLDR):
(DecodeMRRC2):
* capstone/Source/arch/ARM/ARMGenAsmWriter.inc:
* capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc:
* capstone/Source/arch/ARM/ARMGenInstrInfo.inc:
* capstone/Source/arch/ARM/ARMGenRegisterInfo.inc:
* capstone/Source/arch/ARM/ARMInstPrinter.c:
(get_op_access):
(set_mem_access):
(op_addImm):
(ARM_getRegName):
(translateShiftImm):
(printRegImmShift):
(printRegName):
(ARM_printInst):
(printOperand):
(printThumbLdrLabelOperand):
(printSORegRegOperand):
(printSORegImmOperand):
(printAM2PreOrOffsetIndexOp):
(printAddrModeTBB):
(printAddrModeTBH):
(printAddrMode2Operand):
(printAddrMode2OffsetOperand):
(printAM3PreOrOffsetIndexOp):
(printAddrMode3Operand):
(printAddrMode3OffsetOperand):
(printPostIdxImm8Operand):
(printPostIdxRegOperand):
(printPostIdxImm8s4Operand):
(printAddrMode5Operand):
(printAddrMode6Operand):
(printAddrMode7Operand):
(printAddrMode6OffsetOperand):
(printBitfieldInvMaskImmOperand):
(printMemBOption):
(printInstSyncBOption):
(printShiftImmOperand):
(printPKHLSLShiftImm):
(printPKHASRShiftImm):
(printRegisterList):
(printGPRPairOperand):
(printSetendOperand):
(printCPSIMod):
(printCPSIFlag):
(printMSRMaskOperand):
(printBankedRegOperand):
(printPredicateOperand):
(printMandatoryPredicateOperand):
(printSBitModifierOperand):
(printNoHashImmediate):
(printPImmediate):
(printCImmediate):
(printCoprocOptionImm):
(printAdrLabelOperand):
(printThumbS4ImmOperand):
(printThumbSRImm):
(printThumbITMask):
(printThumbAddrModeRROperand):
(printThumbAddrModeImm5SOperand):
(printThumbAddrModeImm5S1Operand):
(printThumbAddrModeImm5S2Operand):
(printThumbAddrModeImm5S4Operand):
(printThumbAddrModeSPOperand):
(printT2SOOperand):
(printAddrModeImm12Operand):
(printT2AddrModeImm8Operand):
(printT2AddrModeImm8s4Operand):
(printT2AddrModeImm0_1020s4Operand):
(printT2AddrModeImm8OffsetOperand):
(printT2AddrModeImm8s4OffsetOperand):
(printT2AddrModeSoRegOperand):
(printFPImmOperand):
(printNEONModImmOperand):
(printImmPlusOneOperand):
(printRotImmOperand):
(printModImmOperand):
(printFBits16):
(printFBits32):
(printVectorIndex):
(printVectorListOne):
(printVectorListTwo):
(printVectorListTwoSpaced):
(printVectorListThree):
(printVectorListFour):
(printVectorListOneAllLanes):
(printVectorListTwoAllLanes):
(printVectorListThreeAllLanes):
(printVectorListFourAllLanes):
(printVectorListTwoSpacedAllLanes):
(printVectorListThreeSpacedAllLanes):
(printVectorListFourSpacedAllLanes):
(printVectorListThreeSpaced):
(printVectorListFourSpaced):
(ARM_addVectorDataType):
(ARM_addVectorDataSize):
(ARM_addReg):
(ARM_addUserMode):
(ARM_addSysReg):
* capstone/Source/arch/ARM/ARMMapping.c:
(ARM_reg_name2):
(ARM_insn_name):
(ARM_rel_branch):
(ARM_blx_to_arm_mode):
(ARM_reg_access):
* capstone/Source/arch/ARM/ARMMapping.h:
* capstone/Source/arch/ARM/ARMMappingInsn.inc:
* capstone/Source/arch/ARM/ARMMappingInsnOp.inc:
* capstone/Source/arch/ARM/ARMModule.c:
(ARM_global_init):
(ARM_option):
(init): Deleted.
(option): Deleted.
(ARM_enable): Deleted.
* capstone/Source/arch/ARM/ARMModule.h: Added.
* capstone/Source/arch/Mips/MipsDisassembler.c:
(getFeatureBits):
(Mips_init):
(readInstruction16):
(readInstruction32):
(MipsDisassembler_getInstruction):
(Mips_getInstruction):
(getReg):
(DecodeINSVE_DF_4):
(DecodeAddiGroupBranch_4):
(DecodeDaddiGroupBranch_4):
(DecodeBlezlGroupBranch_4):
(DecodeBgtzlGroupBranch_4):
(DecodeBgtzGroupBranch_4):
(DecodeBlezGroupBranch_4):
(DecodeCPU16RegsRegisterClass):
(DecodeGPR64RegisterClass):
(DecodeGPRMM16RegisterClass):
(DecodeGPRMM16ZeroRegisterClass):
(DecodeGPRMM16MovePRegisterClass):
(DecodeGPR32RegisterClass):
(DecodePtrRegisterClass):
(DecodeDSPRRegisterClass):
(DecodeFGR64RegisterClass):
(DecodeFGR32RegisterClass):
(DecodeCCRRegisterClass):
(DecodeFCCRegisterClass):
(DecodeCCRegisterClass):
(DecodeFGRCCRegisterClass):
(DecodeMem):
(DecodeCacheOp):
(DecodeCacheOpMM):
(DecodeCacheOpR6):
(DecodeSyncI):
(DecodeMSA128Mem):
(DecodeMemMMImm4):
(DecodeMemMMSPImm5Lsl2):
(DecodeMemMMGPImm7Lsl2):
(DecodeMemMMReglistImm4Lsl2):
(DecodeMemMMImm12):
(DecodeMemMMImm16):
(DecodeFMem):
(DecodeFMem2):
(DecodeFMem3):
(DecodeFMemCop2R6):
(DecodeSpecial3LlSc):
(DecodeHWRegsRegisterClass):
(DecodeAFGR64RegisterClass):
(DecodeACC64DSPRegisterClass):
(DecodeHI32DSPRegisterClass):
(DecodeLO32DSPRegisterClass):
(DecodeMSA128BRegisterClass):
(DecodeMSA128HRegisterClass):
(DecodeMSA128WRegisterClass):
(DecodeMSA128DRegisterClass):
(DecodeMSACtrlRegisterClass):
(DecodeCOP2RegisterClass):
(DecodeBranchTarget):
(DecodeJumpTarget):
(DecodeBranchTarget21):
(DecodeBranchTarget26):
(DecodeBranchTarget7MM):
(DecodeBranchTarget10MM):
(DecodeBranchTargetMM):
(DecodeJumpTargetMM):
(DecodeAddiur2Simm7):
(DecodeUImm6Lsl2):
(DecodeLiSimm7):
(DecodeSimm4):
(DecodeSimm16):
(DecodeLSAImm):
(DecodeInsSize):
(DecodeExtSize):
(DecodeSimm19Lsl2):
(DecodeSimm18Lsl3):
(DecodeSimm9SP):
(DecodeANDI16Imm):
(DecodeUImm5lsl2):
(DecodeRegListOperand):
(DecodeRegListOperand16):
(DecodeMovePRegPair):
(DecodeSimm23Lsl2):
* capstone/Source/arch/Mips/MipsDisassembler.h:
* capstone/Source/arch/Mips/MipsGenAsmWriter.inc:
* capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc:
* capstone/Source/arch/Mips/MipsGenInstrInfo.inc:
* capstone/Source/arch/Mips/MipsGenRegisterInfo.inc:
* capstone/Source/arch/Mips/MipsInstPrinter.c:
(set_mem_access):
(isReg):
(MipsFCCToString):
(printRegName):
(Mips_printInst):
(printOperand):
(printUnsignedImm):
(printUnsignedImm8):
(printMemOperand):
(printMemOperandEA):
(printFCCOperand):
(printRegisterPair):
(printAlias1):
(printAlias2):
(printAlias):
(printRegisterList):
* capstone/Source/arch/Mips/MipsMapping.c:
(Mips_get_insn_id):
(Mips_group_name):
(Mips_map_insn):
(Mips_map_register):
* capstone/Source/arch/Mips/MipsMappingInsn.inc:
* capstone/Source/arch/Mips/MipsModule.c:
(updated_mode):
(Mips_global_init):
(Mips_option):
(init): Deleted.
(option): Deleted.
(Mips_enable): Deleted.
* capstone/Source/arch/Mips/MipsModule.h: Added.
* capstone/Source/capstone.pc.in:
* capstone/Source/cmake.sh: Added.
* capstone/Source/config.mk:
* capstone/Source/cs.c:
(cs_version):
(cs_support):
(cs_errno):
(cs_strerror):
(cs_open):
(cs_close):
(fill_insn):
(skipdata_size):
(cs_option):
(skipdata_opstr):
(cs_disasm):
(cs_disasm_ex):
(cs_free):
(cs_malloc):
(cs_disasm_iter):
(cs_reg_name):
(cs_insn_name):
(cs_group_name):
(cs_insn_group):
(cs_reg_read):
(cs_reg_write):
(cs_op_count):
(cs_op_index):
(cs_regs_access):
(cs_kern_os_calloc): Deleted.
* capstone/Source/cs_priv.h:
* capstone/Source/functions.mk:
* capstone/Source/include/capstone/arm.h:
* capstone/Source/include/capstone/arm64.h:
* capstone/Source/include/capstone/capstone.h:
* capstone/Source/include/capstone/evm.h:
* capstone/Source/include/capstone/m680x.h:
* capstone/Source/include/capstone/m68k.h:
* capstone/Source/include/capstone/mips.h:
* capstone/Source/include/capstone/mos65xx.h: Added.
* capstone/Source/include/capstone/platform.h:
* capstone/Source/include/capstone/ppc.h:
* capstone/Source/include/capstone/sparc.h:
* capstone/Source/include/capstone/systemz.h:
* capstone/Source/include/capstone/tms320c64x.h:
* capstone/Source/include/capstone/x86.h:
* capstone/Source/include/capstone/xcore.h:
* capstone/Source/include/platform.h: Copied from Source/ThirdParty/capstone/Source/include/capstone/platform.h.
* capstone/Source/include/windowsce/stdint.h:
* capstone/Source/make.sh:
* capstone/Source/nmake-x86.bat: Removed.
* capstone/Source/nmake.bat:
* capstone/Source/pkgconfig.mk:
* capstone/Source/utils.c:
(make_id2insn):
(insn_find):
(name2id):
(id2name):
(count_positive):
(count_positive8):
(cs_strdup):
(cs_snprintf):
(arr_exist8):
(arr_exist):
* capstone/Source/utils.h:
* capstone/capstone-Revision.txt:

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@271083 268f45cc-cd09-0410-ab3c-d52691b4dbfc

81 files changed:
Source/ThirdParty/ChangeLog
Source/ThirdParty/capstone/CMakeLists.txt
Source/ThirdParty/capstone/Source/.gitignore
Source/ThirdParty/capstone/Source/.travis.yml
Source/ThirdParty/capstone/Source/CMakeLists.txt
Source/ThirdParty/capstone/Source/COMPILE.TXT
Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT
Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT
Source/ThirdParty/capstone/Source/CREDITS.TXT
Source/ThirdParty/capstone/Source/ChangeLog-capstone
Source/ThirdParty/capstone/Source/HACK.TXT
Source/ThirdParty/capstone/Source/LEB128.h
Source/ThirdParty/capstone/Source/MCDisassembler.h
Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h
Source/ThirdParty/capstone/Source/MCInst.c
Source/ThirdParty/capstone/Source/MCInst.h
Source/ThirdParty/capstone/Source/MCInstrDesc.c
Source/ThirdParty/capstone/Source/MCInstrDesc.h
Source/ThirdParty/capstone/Source/MCRegisterInfo.c
Source/ThirdParty/capstone/Source/MCRegisterInfo.h
Source/ThirdParty/capstone/Source/Makefile
Source/ThirdParty/capstone/Source/MathExtras.h
Source/ThirdParty/capstone/Source/README.md
Source/ThirdParty/capstone/Source/SPONSORS.TXT [new file with mode: 0644]
Source/ThirdParty/capstone/Source/SStream.c
Source/ThirdParty/capstone/Source/SStream.h
Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h
Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h
Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c
Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c
Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c
Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h
Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsn.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMMappingInsnOp.inc
Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c
Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.h [new file with mode: 0644]
Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c
Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h
Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc
Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc
Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc
Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc
Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c
Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c
Source/ThirdParty/capstone/Source/arch/Mips/MipsMappingInsn.inc
Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c
Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.h [new file with mode: 0644]
Source/ThirdParty/capstone/Source/capstone.pc.in
Source/ThirdParty/capstone/Source/cmake.sh [new file with mode: 0755]
Source/ThirdParty/capstone/Source/config.mk
Source/ThirdParty/capstone/Source/cs.c
Source/ThirdParty/capstone/Source/cs_priv.h
Source/ThirdParty/capstone/Source/functions.mk
Source/ThirdParty/capstone/Source/include/capstone/arm.h
Source/ThirdParty/capstone/Source/include/capstone/arm64.h
Source/ThirdParty/capstone/Source/include/capstone/capstone.h
Source/ThirdParty/capstone/Source/include/capstone/evm.h
Source/ThirdParty/capstone/Source/include/capstone/m680x.h
Source/ThirdParty/capstone/Source/include/capstone/m68k.h
Source/ThirdParty/capstone/Source/include/capstone/mips.h
Source/ThirdParty/capstone/Source/include/capstone/mos65xx.h [new file with mode: 0644]
Source/ThirdParty/capstone/Source/include/capstone/platform.h
Source/ThirdParty/capstone/Source/include/capstone/ppc.h
Source/ThirdParty/capstone/Source/include/capstone/sparc.h
Source/ThirdParty/capstone/Source/include/capstone/systemz.h
Source/ThirdParty/capstone/Source/include/capstone/tms320c64x.h
Source/ThirdParty/capstone/Source/include/capstone/x86.h
Source/ThirdParty/capstone/Source/include/capstone/xcore.h
Source/ThirdParty/capstone/Source/include/platform.h [new file with mode: 0644]
Source/ThirdParty/capstone/Source/include/windowsce/stdint.h
Source/ThirdParty/capstone/Source/make.sh
Source/ThirdParty/capstone/Source/nmake-x86.bat [deleted file]
Source/ThirdParty/capstone/Source/nmake.bat
Source/ThirdParty/capstone/Source/pkgconfig.mk
Source/ThirdParty/capstone/Source/utils.c
Source/ThirdParty/capstone/Source/utils.h
Source/ThirdParty/capstone/capstone-Revision.txt

index 14e65afeff0304dd690a4cc07740d8e45f249b0d..56811359500cc96f54e6a2a33a3a5ece52d83830 100644 (file)
@@ -1,3 +1,604 @@
+2020-12-25  Yusuke Suzuki  <ysuzuki@apple.com>
+
+        Update capstone
+        https://bugs.webkit.org/show_bug.cgi?id=219941
+
+        Reviewed by Michael Catanzaro.
+
+        * capstone/CMakeLists.txt:
+        * capstone/Source/.gitignore:
+        * capstone/Source/.travis.yml:
+        * capstone/Source/CMakeLists.txt:
+        * capstone/Source/COMPILE.TXT:
+        * capstone/Source/COMPILE_CMAKE.TXT:
+        * capstone/Source/COMPILE_MSVC.TXT:
+        * capstone/Source/CREDITS.TXT:
+        * capstone/Source/ChangeLog-capstone:
+        * capstone/Source/HACK.TXT:
+        * capstone/Source/LEB128.h:
+        (decodeULEB128):
+        * capstone/Source/MCDisassembler.h:
+        * capstone/Source/MCFixedLenDisassembler.h:
+        * capstone/Source/MCInst.c:
+        (MCInst_Init):
+        (MCInst_clear):
+        (MCInst_insert0):
+        (MCInst_setOpcode):
+        (MCInst_setOpcodePub):
+        (MCInst_getOpcode):
+        (MCInst_getOpcodePub):
+        (MCInst_getOperand):
+        (MCInst_getNumOperands):
+        (MCInst_addOperand2):
+        (MCOperand_isValid):
+        (MCOperand_isReg):
+        (MCOperand_isImm):
+        (MCOperand_isFPImm):
+        (MCOperand_getReg):
+        (MCOperand_setReg):
+        (MCOperand_getImm):
+        (MCOperand_setImm):
+        (MCOperand_getFPImm):
+        (MCOperand_setFPImm):
+        (MCOperand_CreateReg1):
+        (MCOperand_CreateReg0):
+        (MCOperand_CreateImm1):
+        (MCOperand_CreateImm0):
+        (MCOperand_Init): Deleted.
+        * capstone/Source/MCInst.h:
+        * capstone/Source/MCInstrDesc.c:
+        (MCOperandInfo_isPredicate):
+        (MCOperandInfo_isOptionalDef):
+        * capstone/Source/MCInstrDesc.h:
+        * capstone/Source/MCRegisterInfo.c:
+        (MCRegisterInfo_InitMCRegisterInfo):
+        (DiffListIterator_init):
+        (DiffListIterator_getVal):
+        (DiffListIterator_next):
+        (DiffListIterator_isValid):
+        (MCRegisterInfo_getMatchingSuperReg):
+        (MCRegisterInfo_getSubReg):
+        (MCRegisterInfo_getRegClass):
+        (MCRegisterClass_contains):
+        * capstone/Source/MCRegisterInfo.h:
+        * capstone/Source/Makefile:
+        * capstone/Source/MathExtras.h:
+        (Hi_32):
+        (Lo_32):
+        (isUIntN):
+        (isMask_32):
+        (isMask_64):
+        (isShiftedMask_32):
+        (isShiftedMask_64):
+        (isPowerOf2_32):
+        (CountLeadingZeros_32):
+        (CountLeadingOnes_32):
+        (CountLeadingZeros_64):
+        (CountLeadingOnes_64):
+        (CountTrailingZeros_32):
+        (CountTrailingOnes_32):
+        (CountTrailingZeros_64):
+        (CountTrailingOnes_64):
+        (CountPopulation_32):
+        (CountPopulation_64):
+        (Log2_32):
+        (Log2_64):
+        (Log2_32_Ceil):
+        (Log2_64_Ceil):
+        (GreatestCommonDivisor64):
+        (BitsToDouble):
+        (BitsToFloat):
+        (DoubleToBits):
+        (FloatToBits):
+        (MinAlign):
+        (NextPowerOf2):
+        (RoundUpToAlignment):
+        (OffsetToAlignment):
+        (abs64):
+        (SignExtend32):
+        (SignExtend64):
+        (countLeadingZeros):
+        * capstone/Source/README.md:
+        * capstone/Source/SPONSORS.TXT: Added.
+        * capstone/Source/SStream.c:
+        (SStream_Init):
+        (SStream_concat0):
+        (SStream_concat):
+        (printInt64Bang):
+        (printUInt64Bang):
+        (printInt64):
+        (printInt32BangDec):
+        (printInt32Bang):
+        (printInt32):
+        (printUInt32Bang):
+        (printUInt32):
+        * capstone/Source/SStream.h:
+        * capstone/Source/arch/ARM/ARMAddressingModes.h:
+        (ARM_AM_getAddrOpcStr):
+        (ARM_AM_getShiftOpcStr):
+        (ARM_AM_getShiftOpcEncoding):
+        (ARM_AM_getAMSubModeStr):
+        (rotr32):
+        (rotl32):
+        (getSORegOpc):
+        (getSORegOffset):
+        (ARM_AM_getSORegShOp):
+        (getSOImmValImm):
+        (getSOImmValRot):
+        (getSOImmValRotate):
+        (getSOImmVal):
+        (isSOImmTwoPartVal):
+        (getSOImmTwoPartFirst):
+        (getSOImmTwoPartSecond):
+        (getThumbImmValShift):
+        (isThumbImmShiftedVal):
+        (getThumbImm16ValShift):
+        (isThumbImm16ShiftedVal):
+        (getThumbImmNonShiftedVal):
+        (getT2SOImmValSplatVal):
+        (getT2SOImmValRotateVal):
+        (getT2SOImmVal):
+        (getT2SOImmValRotate):
+        (isT2SOImmTwoPartVal):
+        (getT2SOImmTwoPartFirst):
+        (getT2SOImmTwoPartSecond):
+        (ARM_AM_getAM2Opc):
+        (getAM2Offset):
+        (getAM2Op):
+        (getAM2ShiftOpc):
+        (getAM2IdxMode):
+        (getAM3Opc):
+        (getAM3Offset):
+        (getAM3Op):
+        (getAM3IdxMode):
+        (getAM4SubMode):
+        (getAM4ModeImm):
+        (ARM_AM_getAM5Opc):
+        (ARM_AM_getAM5Offset):
+        (ARM_AM_getAM5Op):
+        (createNEONModImm):
+        (getNEONModImmOpCmode):
+        (getNEONModImmVal):
+        (ARM_AM_decodeNEONModImm):
+        (getFPImmFloat):
+        * capstone/Source/arch/ARM/ARMBaseInfo.h:
+        (ARMCC_getOppositeCondition):
+        (ARMCC_ARMCondCodeToString):
+        (ARM_PROC_IFlagsToString):
+        (ARM_PROC_IModToString):
+        (ARM_MB_MemBOptToString):
+        (ARM_ISB_InstSyncBOptToString):
+        (isARMLowRegister):
+        (ARMII_AddrModeToString):
+        * capstone/Source/arch/ARM/ARMDisassembler.c:
+        (ITStatus_push_back):
+        (ITStatus_instrInITBlock):
+        (ITStatus_instrLastInITBlock):
+        (ITStatus_getITCC):
+        (ITStatus_advanceITState):
+        (ITStatus_setITState):
+        (Check):
+        (ARM_getFeatureBits):
+        (DecodePredicateOperand):
+        (ARM_init):
+        (checkDecodedInstruction):
+        (_ARM_getInstruction):
+        (AddThumb1SBit):
+        (AddThumbPredicate):
+        (UpdateThumbVFPPredicate):
+        (_Thumb_getInstruction):
+        (Thumb_getInstruction):
+        (ARM_getInstruction):
+        (DecodeGPRnopcRegisterClass):
+        (DecodeGPRwithAPSRRegisterClass):
+        (DecodetGPRRegisterClass):
+        (DecodetcGPRRegisterClass):
+        (DecoderGPRRegisterClass):
+        (DecodeDPRRegisterClass):
+        (DecodeDPR_8RegisterClass):
+        (DecodeDPR_VFP2RegisterClass):
+        (DecodeDPairRegisterClass):
+        (DecodeCCOutOperand):
+        (DecodeSORegImmOperand):
+        (DecodeSORegRegOperand):
+        (DecodeRegListOperand):
+        (DecodeSPRRegListOperand):
+        (DecodeDPRRegListOperand):
+        (DecodeBitfieldMaskOperand):
+        (DecodeCopMemInstruction):
+        (DecodeAddrMode2IdxInstruction):
+        (DecodeSORegMemOperand):
+        (DecodeAddrMode3Instruction):
+        (DecodeRFEInstruction):
+        (DecodeQADDInstruction):
+        (DecodeMemMultipleWritebackInstruction):
+        (DecodeCPSInstruction):
+        (DecodeT2CPSInstruction):
+        (DecodeT2MOVTWInstruction):
+        (DecodeArmMOVTWInstruction):
+        (DecodeSMLAInstruction):
+        (DecodeAddrModeImm12Operand):
+        (DecodeAddrMode5Operand):
+        (DecodeAddrMode7Operand):
+        (DecodeT2BInstruction):
+        (DecodeBranchImmInstruction):
+        (DecodeAddrMode6Operand):
+        (DecodeVLDInstruction):
+        (DecodeVLDST1Instruction):
+        (DecodeVLDST2Instruction):
+        (DecodeVLDST3Instruction):
+        (DecodeVLDST4Instruction):
+        (DecodeVSTInstruction):
+        (DecodeVLD1DupInstruction):
+        (DecodeVLD2DupInstruction):
+        (DecodeVLD3DupInstruction):
+        (DecodeVLD4DupInstruction):
+        (DecodeNEONModImmInstruction):
+        (DecodeVSHLMaxInstruction):
+        (DecodeShiftRight8Imm):
+        (DecodeShiftRight16Imm):
+        (DecodeShiftRight32Imm):
+        (DecodeShiftRight64Imm):
+        (DecodeTBLInstruction):
+        (DecodeThumbAddSpecialReg):
+        (DecodeThumbBROperand):
+        (DecodeT2BROperand):
+        (DecodeThumbCmpBROperand):
+        (DecodeThumbAddrModeRR):
+        (DecodeThumbAddrModeIS):
+        (DecodeThumbAddrModePC):
+        (DecodeThumbAddrModeSP):
+        (DecodeT2AddrModeSOReg):
+        (DecodeT2LoadShift):
+        (DecodeT2LoadImm8):
+        (DecodeT2LoadImm12):
+        (DecodeT2LoadT):
+        (DecodeT2LoadLabel):
+        (DecodeT2Imm8S4):
+        (DecodeT2AddrModeImm8s4):
+        (DecodeT2AddrModeImm0_1020s4):
+        (DecodeT2Imm8):
+        (DecodeT2AddrModeImm8):
+        (DecodeT2LdStPre):
+        (DecodeT2AddrModeImm12):
+        (DecodeThumbAddSPImm):
+        (DecodeThumbAddSPReg):
+        (DecodeThumbCPS):
+        (DecodePostIdxReg):
+        (DecodeThumbBLXOffset):
+        (DecodeCoprocessor):
+        (DecodeThumbTableBranch):
+        (DecodeThumb2BCCInstruction):
+        (DecodeT2SOImm):
+        (DecodeThumbBCCTargetOperand):
+        (DecodeThumbBLTargetOperand):
+        (DecodeMemBarrierOption):
+        (DecodeInstSyncBarrierOption):
+        (DecodeMSRMask):
+        (DecodeBankedReg):
+        (DecodeDoubleRegLoad):
+        (DecodeDoubleRegStore):
+        (DecodeLDRPreImm):
+        (DecodeLDRPreReg):
+        (DecodeSTRPreImm):
+        (DecodeSTRPreReg):
+        (DecodeVLD1LN):
+        (DecodeVST1LN):
+        (DecodeVLD2LN):
+        (DecodeVST2LN):
+        (DecodeVLD3LN):
+        (DecodeVST3LN):
+        (DecodeVLD4LN):
+        (DecodeVST4LN):
+        (DecodeVMOVSRR):
+        (DecodeVMOVRRS):
+        (DecodeIT):
+        (DecodeT2LDRDPreInstruction):
+        (DecodeT2STRDPreInstruction):
+        (DecodeT2Adr):
+        (DecodeT2ShifterImmOperand):
+        (DecodeSwap):
+        (DecodeVCVTD):
+        (DecodeVCVTQ):
+        (DecodeLDR):
+        (DecodeMRRC2):
+        * capstone/Source/arch/ARM/ARMGenAsmWriter.inc:
+        * capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc:
+        * capstone/Source/arch/ARM/ARMGenInstrInfo.inc:
+        * capstone/Source/arch/ARM/ARMGenRegisterInfo.inc:
+        * capstone/Source/arch/ARM/ARMInstPrinter.c:
+        (get_op_access):
+        (set_mem_access):
+        (op_addImm):
+        (ARM_getRegName):
+        (translateShiftImm):
+        (printRegImmShift):
+        (printRegName):
+        (ARM_printInst):
+        (printOperand):
+        (printThumbLdrLabelOperand):
+        (printSORegRegOperand):
+        (printSORegImmOperand):
+        (printAM2PreOrOffsetIndexOp):
+        (printAddrModeTBB):
+        (printAddrModeTBH):
+        (printAddrMode2Operand):
+        (printAddrMode2OffsetOperand):
+        (printAM3PreOrOffsetIndexOp):
+        (printAddrMode3Operand):
+        (printAddrMode3OffsetOperand):
+        (printPostIdxImm8Operand):
+        (printPostIdxRegOperand):
+        (printPostIdxImm8s4Operand):
+        (printAddrMode5Operand):
+        (printAddrMode6Operand):
+        (printAddrMode7Operand):
+        (printAddrMode6OffsetOperand):
+        (printBitfieldInvMaskImmOperand):
+        (printMemBOption):
+        (printInstSyncBOption):
+        (printShiftImmOperand):
+        (printPKHLSLShiftImm):
+        (printPKHASRShiftImm):
+        (printRegisterList):
+        (printGPRPairOperand):
+        (printSetendOperand):
+        (printCPSIMod):
+        (printCPSIFlag):
+        (printMSRMaskOperand):
+        (printBankedRegOperand):
+        (printPredicateOperand):
+        (printMandatoryPredicateOperand):
+        (printSBitModifierOperand):
+        (printNoHashImmediate):
+        (printPImmediate):
+        (printCImmediate):
+        (printCoprocOptionImm):
+        (printAdrLabelOperand):
+        (printThumbS4ImmOperand):
+        (printThumbSRImm):
+        (printThumbITMask):
+        (printThumbAddrModeRROperand):
+        (printThumbAddrModeImm5SOperand):
+        (printThumbAddrModeImm5S1Operand):
+        (printThumbAddrModeImm5S2Operand):
+        (printThumbAddrModeImm5S4Operand):
+        (printThumbAddrModeSPOperand):
+        (printT2SOOperand):
+        (printAddrModeImm12Operand):
+        (printT2AddrModeImm8Operand):
+        (printT2AddrModeImm8s4Operand):
+        (printT2AddrModeImm0_1020s4Operand):
+        (printT2AddrModeImm8OffsetOperand):
+        (printT2AddrModeImm8s4OffsetOperand):
+        (printT2AddrModeSoRegOperand):
+        (printFPImmOperand):
+        (printNEONModImmOperand):
+        (printImmPlusOneOperand):
+        (printRotImmOperand):
+        (printModImmOperand):
+        (printFBits16):
+        (printFBits32):
+        (printVectorIndex):
+        (printVectorListOne):
+        (printVectorListTwo):
+        (printVectorListTwoSpaced):
+        (printVectorListThree):
+        (printVectorListFour):
+        (printVectorListOneAllLanes):
+        (printVectorListTwoAllLanes):
+        (printVectorListThreeAllLanes):
+        (printVectorListFourAllLanes):
+        (printVectorListTwoSpacedAllLanes):
+        (printVectorListThreeSpacedAllLanes):
+        (printVectorListFourSpacedAllLanes):
+        (printVectorListThreeSpaced):
+        (printVectorListFourSpaced):
+        (ARM_addVectorDataType):
+        (ARM_addVectorDataSize):
+        (ARM_addReg):
+        (ARM_addUserMode):
+        (ARM_addSysReg):
+        * capstone/Source/arch/ARM/ARMMapping.c:
+        (ARM_reg_name2):
+        (ARM_insn_name):
+        (ARM_rel_branch):
+        (ARM_blx_to_arm_mode):
+        (ARM_reg_access):
+        * capstone/Source/arch/ARM/ARMMapping.h:
+        * capstone/Source/arch/ARM/ARMMappingInsn.inc:
+        * capstone/Source/arch/ARM/ARMMappingInsnOp.inc:
+        * capstone/Source/arch/ARM/ARMModule.c:
+        (ARM_global_init):
+        (ARM_option):
+        (init): Deleted.
+        (option): Deleted.
+        (ARM_enable): Deleted.
+        * capstone/Source/arch/ARM/ARMModule.h: Added.
+        * capstone/Source/arch/Mips/MipsDisassembler.c:
+        (getFeatureBits):
+        (Mips_init):
+        (readInstruction16):
+        (readInstruction32):
+        (MipsDisassembler_getInstruction):
+        (Mips_getInstruction):
+        (getReg):
+        (DecodeINSVE_DF_4):
+        (DecodeAddiGroupBranch_4):
+        (DecodeDaddiGroupBranch_4):
+        (DecodeBlezlGroupBranch_4):
+        (DecodeBgtzlGroupBranch_4):
+        (DecodeBgtzGroupBranch_4):
+        (DecodeBlezGroupBranch_4):
+        (DecodeCPU16RegsRegisterClass):
+        (DecodeGPR64RegisterClass):
+        (DecodeGPRMM16RegisterClass):
+        (DecodeGPRMM16ZeroRegisterClass):
+        (DecodeGPRMM16MovePRegisterClass):
+        (DecodeGPR32RegisterClass):
+        (DecodePtrRegisterClass):
+        (DecodeDSPRRegisterClass):
+        (DecodeFGR64RegisterClass):
+        (DecodeFGR32RegisterClass):
+        (DecodeCCRRegisterClass):
+        (DecodeFCCRegisterClass):
+        (DecodeCCRegisterClass):
+        (DecodeFGRCCRegisterClass):
+        (DecodeMem):
+        (DecodeCacheOp):
+        (DecodeCacheOpMM):
+        (DecodeCacheOpR6):
+        (DecodeSyncI):
+        (DecodeMSA128Mem):
+        (DecodeMemMMImm4):
+        (DecodeMemMMSPImm5Lsl2):
+        (DecodeMemMMGPImm7Lsl2):
+        (DecodeMemMMReglistImm4Lsl2):
+        (DecodeMemMMImm12):
+        (DecodeMemMMImm16):
+        (DecodeFMem):
+        (DecodeFMem2):
+        (DecodeFMem3):
+        (DecodeFMemCop2R6):
+        (DecodeSpecial3LlSc):
+        (DecodeHWRegsRegisterClass):
+        (DecodeAFGR64RegisterClass):
+        (DecodeACC64DSPRegisterClass):
+        (DecodeHI32DSPRegisterClass):
+        (DecodeLO32DSPRegisterClass):
+        (DecodeMSA128BRegisterClass):
+        (DecodeMSA128HRegisterClass):
+        (DecodeMSA128WRegisterClass):
+        (DecodeMSA128DRegisterClass):
+        (DecodeMSACtrlRegisterClass):
+        (DecodeCOP2RegisterClass):
+        (DecodeBranchTarget):
+        (DecodeJumpTarget):
+        (DecodeBranchTarget21):
+        (DecodeBranchTarget26):
+        (DecodeBranchTarget7MM):
+        (DecodeBranchTarget10MM):
+        (DecodeBranchTargetMM):
+        (DecodeJumpTargetMM):
+        (DecodeAddiur2Simm7):
+        (DecodeUImm6Lsl2):
+        (DecodeLiSimm7):
+        (DecodeSimm4):
+        (DecodeSimm16):
+        (DecodeLSAImm):
+        (DecodeInsSize):
+        (DecodeExtSize):
+        (DecodeSimm19Lsl2):
+        (DecodeSimm18Lsl3):
+        (DecodeSimm9SP):
+        (DecodeANDI16Imm):
+        (DecodeUImm5lsl2):
+        (DecodeRegListOperand):
+        (DecodeRegListOperand16):
+        (DecodeMovePRegPair):
+        (DecodeSimm23Lsl2):
+        * capstone/Source/arch/Mips/MipsDisassembler.h:
+        * capstone/Source/arch/Mips/MipsGenAsmWriter.inc:
+        * capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc:
+        * capstone/Source/arch/Mips/MipsGenInstrInfo.inc:
+        * capstone/Source/arch/Mips/MipsGenRegisterInfo.inc:
+        * capstone/Source/arch/Mips/MipsInstPrinter.c:
+        (set_mem_access):
+        (isReg):
+        (MipsFCCToString):
+        (printRegName):
+        (Mips_printInst):
+        (printOperand):
+        (printUnsignedImm):
+        (printUnsignedImm8):
+        (printMemOperand):
+        (printMemOperandEA):
+        (printFCCOperand):
+        (printRegisterPair):
+        (printAlias1):
+        (printAlias2):
+        (printAlias):
+        (printRegisterList):
+        * capstone/Source/arch/Mips/MipsMapping.c:
+        (Mips_get_insn_id):
+        (Mips_group_name):
+        (Mips_map_insn):
+        (Mips_map_register):
+        * capstone/Source/arch/Mips/MipsMappingInsn.inc:
+        * capstone/Source/arch/Mips/MipsModule.c:
+        (updated_mode):
+        (Mips_global_init):
+        (Mips_option):
+        (init): Deleted.
+        (option): Deleted.
+        (Mips_enable): Deleted.
+        * capstone/Source/arch/Mips/MipsModule.h: Added.
+        * capstone/Source/capstone.pc.in:
+        * capstone/Source/cmake.sh: Added.
+        * capstone/Source/config.mk:
+        * capstone/Source/cs.c:
+        (cs_version):
+        (cs_support):
+        (cs_errno):
+        (cs_strerror):
+        (cs_open):
+        (cs_close):
+        (fill_insn):
+        (skipdata_size):
+        (cs_option):
+        (skipdata_opstr):
+        (cs_disasm):
+        (cs_disasm_ex):
+        (cs_free):
+        (cs_malloc):
+        (cs_disasm_iter):
+        (cs_reg_name):
+        (cs_insn_name):
+        (cs_group_name):
+        (cs_insn_group):
+        (cs_reg_read):
+        (cs_reg_write):
+        (cs_op_count):
+        (cs_op_index):
+        (cs_regs_access):
+        (cs_kern_os_calloc): Deleted.
+        * capstone/Source/cs_priv.h:
+        * capstone/Source/functions.mk:
+        * capstone/Source/include/capstone/arm.h:
+        * capstone/Source/include/capstone/arm64.h:
+        * capstone/Source/include/capstone/capstone.h:
+        * capstone/Source/include/capstone/evm.h:
+        * capstone/Source/include/capstone/m680x.h:
+        * capstone/Source/include/capstone/m68k.h:
+        * capstone/Source/include/capstone/mips.h:
+        * capstone/Source/include/capstone/mos65xx.h: Added.
+        * capstone/Source/include/capstone/platform.h:
+        * capstone/Source/include/capstone/ppc.h:
+        * capstone/Source/include/capstone/sparc.h:
+        * capstone/Source/include/capstone/systemz.h:
+        * capstone/Source/include/capstone/tms320c64x.h:
+        * capstone/Source/include/capstone/x86.h:
+        * capstone/Source/include/capstone/xcore.h:
+        * capstone/Source/include/platform.h: Copied from Source/ThirdParty/capstone/Source/include/capstone/platform.h.
+        * capstone/Source/include/windowsce/stdint.h:
+        * capstone/Source/make.sh:
+        * capstone/Source/nmake-x86.bat: Removed.
+        * capstone/Source/nmake.bat:
+        * capstone/Source/pkgconfig.mk:
+        * capstone/Source/utils.c:
+        (make_id2insn):
+        (insn_find):
+        (name2id):
+        (id2name):
+        (count_positive):
+        (count_positive8):
+        (cs_strdup):
+        (cs_snprintf):
+        (arr_exist8):
+        (arr_exist):
+        * capstone/Source/utils.h:
+        * capstone/capstone-Revision.txt:
+
 2020-12-21  Ryan Hostetler  <rhost@apple.com>
 
         $(findstring iphone,$(SDKROOT)) fails when SDKROOT is not lowercase
index 06fc06a3f3befe53ec3e57547dceb56adb6844bc..b1bea095b689a2eff50715b9b16cfe49de4cc01f 100644 (file)
@@ -1,3 +1,16 @@
+if(POLICY CMP0042)
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html
+  cmake_policy(SET CMP0042 NEW)
+endif(POLICY CMP0042)
+
+if (POLICY CMP0048)
+  # use old policy to honor version set using VERSION_* variables to preserve backwards
+  # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and
+  # set VERSION using project(capstone VERSION 4.0.0).
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html
+  cmake_policy (SET CMP0048 OLD)
+endif()
+
 add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
 
 ## sources
@@ -26,6 +39,7 @@ set(HEADERS_COMMON
     Source/include/capstone/arm64.h
     Source/include/capstone/arm.h
     Source/include/capstone/capstone.h
+    Source/include/capstone/evm.h
     Source/include/capstone/mips.h
     Source/include/capstone/ppc.h
     Source/include/capstone/x86.h
@@ -35,10 +49,10 @@ set(HEADERS_COMMON
     Source/include/capstone/m68k.h
     Source/include/capstone/tms320c64x.h
     Source/include/capstone/m680x.h
+    Source/include/capstone/mos65xx.h
     Source/include/capstone/platform.h
     )
 
-
 ## architecture support
 if (WTF_CPU_ARM)
     add_definitions(-DCAPSTONE_HAS_ARM)
@@ -62,6 +76,18 @@ if (WTF_CPU_ARM)
         Source/arch/ARM/ARMMappingInsn.inc
         Source/arch/ARM/ARMMappingInsnOp.inc
         )
+    set(HEADERS_ARM
+        Source/arch/ARM/ARMAddressingModes.h
+        Source/arch/ARM/ARMBaseInfo.h
+        Source/arch/ARM/ARMDisassembler.h
+        Source/arch/ARM/ARMGenAsmWriter.inc
+        Source/arch/ARM/ARMGenDisassemblerTables.inc
+        Source/arch/ARM/ARMGenInstrInfo.inc
+        Source/arch/ARM/ARMGenRegisterInfo.inc
+        Source/arch/ARM/ARMGenSubtargetInfo.inc
+        Source/arch/ARM/ARMInstPrinter.h
+        Source/arch/ARM/ARMMapping.h
+        )
 endif ()
 
 if (WTF_CPU_MIPS)
@@ -83,23 +109,29 @@ if (WTF_CPU_MIPS)
         Source/arch/Mips/MipsMapping.h
         Source/arch/Mips/MipsMappingInsn.inc
         )
+    set(HEADERS_MIPS
+        Source/arch/Mips/MipsDisassembler.h
+        Source/arch/Mips/MipsGenAsmWriter.inc
+        Source/arch/Mips/MipsGenDisassemblerTables.inc
+        Source/arch/Mips/MipsGenInstrInfo.inc
+        Source/arch/Mips/MipsGenRegisterInfo.inc
+        Source/arch/Mips/MipsGenSubtargetInfo.inc
+        Source/arch/Mips/MipsInstPrinter.h
+        Source/arch/Mips/MipsMapping.h
+        )
 endif ()
 
 set(capstone_SOURCES
     ${SOURCES_ENGINE}
     ${SOURCES_ARM}
-    ${SOURCES_ARM64}
     ${SOURCES_MIPS}
-    ${SOURCES_X86}
     )
 
 set(capstone_HEADERS
     ${HEADERS_COMMON}
     ${HEADERS_ENGINE}
     ${HEADERS_ARM}
-    ${HEADERS_ARM64}
     ${HEADERS_MIPS}
-    ${HEADERS_X86}
     )
 
 set(capstone_INCLUDE_DIRECTORIES "${THIRDPARTY_DIR}/capstone/Source/include")
index ec5bc8d6e1daac63bfacb3a9cb6c8cc27397af7b..da89f952c8a108818bc08bbf84d64ac84b11d433 100644 (file)
@@ -68,6 +68,10 @@ tests/test_m68k
 tests/test_tms320c64x
 tests/test_m680x
 tests/test_evm
+tests/test_mos65xx
+
+# regress binaries
+suite/regress/invalid_read_in_print_operand
 
 # vim tmp file
 *.swp
@@ -95,6 +99,9 @@ build*/
 *.VC.db
 *.VC.opendb
 
+# CMake build directories
+build*/
+
 # Xcode
 xcode/Capstone.xcodeproj/xcuserdata
 xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
@@ -104,8 +111,14 @@ test_arm_regression
 test_arm_regression.o
 fuzz_harness
 test_iter_benchmark
+fuzz_bindisasm
+fuzz_disasm
+capstone_get_setup
 
 
 *.s
 
 cstool/cstool
+
+# android
+android-ndk-*
index aa8f5a136ebac49a9d5d88e77869fba08474c9ba..42a6322470d944e88eea08c577c8d125bfe91651 100644 (file)
@@ -2,15 +2,74 @@ language: cpp
 sudo: false
 before_install:
         - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
+before_script:
+        - wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
+        - unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
+        # TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default
+        - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka
+        - chmod +x suite/cstest/build_cstest.sh
 script:
         - ./make.sh
         - make check
+        - sudo make install
         - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
         - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
-        - cd bindings/python && make check
+        - if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi
 compiler:
         - clang
         - gcc
 os:
         - linux
         - osx
+matrix:
+    include:
+        - name: xenial gcc
+          os: linux
+          dist: xenial
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: bionic gcc (ARM64)
+          arch: arm64
+          os: linux
+          dist: bionic
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+                - unzip
+        - name: bionic gcc (System Z)
+          arch: s390x
+          os: linux
+          dist: bionic
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: xenial clang
+          os: linux
+          dist: xenial
+          compiler: clang
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: fuzza
+          env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" LDFLAGS="-fsanitize=address" NOPYTEST=true
+          compiler: clang
+          os: linux
+        - name: fuzzm
+          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" LDFLAGS="-fsanitize=memory" NOPYTEST=true
+          compiler: clang
+          os: linux
+        - name: fuzzu
+          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer" LDFLAGS="-fsanitize=undefined" NOPYTEST=true
+          compiler: clang
+          os: linux
index 84884660b0e6d91fdc68f05962c88c61b56e589b..070ab1257b382c8bef03fe1800ce4095ff78bec2 100644 (file)
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 2.6)
 project(capstone)
 
-set(VERSION_MAJOR 4)
+set(VERSION_MAJOR 5)
 set(VERSION_MINOR 0)
 set(VERSION_PATCH 0)
 
@@ -27,9 +27,11 @@ option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
 option(CAPSTONE_BUILD_TESTS "Build tests" ON)
 option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON)
 option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
+option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
+option(CAPSTONE_INSTALL "Generate install target" ON)
 
-set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM)
+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX)
 
 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@@ -37,10 +39,10 @@ math(EXPR count "${count}-1")
 foreach(i RANGE ${count})
   list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture)
   list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label)
-  option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ON)
+  option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ${CAPSTONE_ARCHITECTURE_DEFAULT})
 endforeach(i)
 
-# propagate achitecture support variables to preprocessor
+# propagate architecture support variables to preprocessor
 foreach(supported_architecture ${SUPPORTED_ARCHITECTURES})
   set(option_name "CAPSTONE_${supported_architecture}_SUPPORT")
   if(${option_name})
@@ -102,6 +104,7 @@ set(HEADERS_COMMON
     include/capstone/arm64.h
     include/capstone/arm.h
     include/capstone/capstone.h
+    include/capstone/evm.h
     include/capstone/mips.h
     include/capstone/ppc.h
     include/capstone/x86.h
@@ -111,10 +114,10 @@ set(HEADERS_COMMON
     include/capstone/m68k.h
     include/capstone/tms320c64x.h
     include/capstone/m680x.h
+    include/capstone/mos65xx.h
     include/capstone/platform.h
     )
 
-
 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
 
 ## architecture support
@@ -140,6 +143,18 @@ if (CAPSTONE_ARM_SUPPORT)
         arch/ARM/ARMMappingInsn.inc
         arch/ARM/ARMMappingInsnOp.inc
         )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        )
     set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
 endif ()
 
@@ -165,6 +180,18 @@ if (CAPSTONE_ARM64_SUPPORT)
         arch/AArch64/AArch64Mapping.h
         arch/AArch64/AArch64MappingInsn.inc
         )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        )
     set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
 endif ()
 
@@ -187,6 +214,16 @@ if (CAPSTONE_MIPS_SUPPORT)
         arch/Mips/MipsMapping.h
         arch/Mips/MipsMappingInsn.inc
         )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        )
     set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
 endif ()
 
@@ -210,6 +247,17 @@ if (CAPSTONE_PPC_SUPPORT)
         arch/PowerPC/PPCMappingInsn.inc
         arch/PowerPC/PPCPredicates.h
         )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCPredicates.h
+        )
     set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
 endif ()
 
@@ -243,6 +291,23 @@ if (CAPSTONE_X86_SUPPORT)
         arch/X86/X86MappingInsnOp_reduce.inc
         arch/X86/X86MappingInsn_reduce.inc
         )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        )
     if (NOT CAPSTONE_BUILD_DIET)
         set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
     endif ()
@@ -256,7 +321,7 @@ if (CAPSTONE_SPARC_SUPPORT)
         arch/Sparc/SparcInstPrinter.c
         arch/Sparc/SparcMapping.c
         arch/Sparc/SparcModule.c
-    )
+        )
     set(HEADERS_SPARC
         arch/Sparc/Sparc.h
         arch/Sparc/SparcDisassembler.h
@@ -278,13 +343,14 @@ if (CAPSTONE_SYSZ_SUPPORT)
         arch/SystemZ/SystemZDisassembler.c
         arch/SystemZ/SystemZInstPrinter.c
         arch/SystemZ/SystemZMapping.c
-        arch/SystemZ/SystemZMCTargetDesc.c
         arch/SystemZ/SystemZModule.c
-    )
+        arch/SystemZ/SystemZMCTargetDesc.c
+        )
     set(HEADERS_SYSZ
         arch/SystemZ/SystemZDisassembler.h
         arch/SystemZ/SystemZGenAsmWriter.inc
         arch/SystemZ/SystemZGenDisassemblerTables.inc
+        arch/SystemZ/SystemZGenInsnNameMaps.inc
         arch/SystemZ/SystemZGenInstrInfo.inc
         arch/SystemZ/SystemZGenRegisterInfo.inc
         arch/SystemZ/SystemZGenSubtargetInfo.inc
@@ -303,7 +369,7 @@ if (CAPSTONE_XCORE_SUPPORT)
         arch/XCore/XCoreInstPrinter.c
         arch/XCore/XCoreMapping.c
         arch/XCore/XCoreModule.c
-    )
+        )
     set(HEADERS_XCORE
         arch/XCore/XCoreDisassembler.h
         arch/XCore/XCoreGenAsmWriter.inc
@@ -320,12 +386,12 @@ endif ()
 if (CAPSTONE_M68K_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_M68K)
     set(SOURCES_M68K
-               arch/M68K/M68KDisassembler.c
-               arch/M68K/M68KInstPrinter.c
-               arch/M68K/M68KModule.c
+        arch/M68K/M68KDisassembler.c
+        arch/M68K/M68KInstPrinter.c
+        arch/M68K/M68KModule.c
     )
     set(HEADERS_M68K
-               arch/M68K/M68KDisassembler.h
+        arch/M68K/M68KDisassembler.h
         )
     set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c)
 endif ()
@@ -353,14 +419,14 @@ endif ()
 if (CAPSTONE_M680X_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_M680X)
     set(SOURCES_M680X
-               arch/M680X/M680XDisassembler.c
-               arch/M680X/M680XInstPrinter.c
-               arch/M680X/M680XModule.c
+        arch/M680X/M680XDisassembler.c
+        arch/M680X/M680XInstPrinter.c
+        arch/M680X/M680XModule.c
     )
     set(HEADERS_M680X
-               arch/M680X/M680XInstPrinter.h
-               arch/M680X/M680XDisassembler.h
-               arch/M680X/M680XDisassemblerInternals.h
+        arch/M680X/M680XInstPrinter.h
+        arch/M680X/M680XDisassembler.h
+        arch/M680X/M680XDisassemblerInternals.h
         )
     set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c)
 endif ()
@@ -382,6 +448,17 @@ if (CAPSTONE_EVM_SUPPORT)
     set(TEST_SOURCES ${TEST_SOURCES} test_evm.c)
 endif ()
 
+if (CAPSTONE_MOS65XX_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_MOS65XX)
+    set(SOURCES_MOS65XX
+            arch/MOS65XX/MOS65XXModule.c
+            arch/MOS65XX/MOS65XXDisassembler.c)
+    set(HEADERS_SOURCES_MOS65XX
+            arch/MOS65XX/MOS65XXDisassembler.h
+    )
+    set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c)
+endif ()
+
 if (CAPSTONE_OSXKERNEL_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif ()
@@ -400,6 +477,7 @@ set(ALL_SOURCES
     ${SOURCES_TMS320C64X}
     ${SOURCES_M680X}
     ${SOURCES_EVM}
+    ${SOURCES_MOS65XX}
     )
 
 set(ALL_HEADERS
@@ -417,6 +495,7 @@ set(ALL_HEADERS
     ${HEADERS_TMS320C64X}
     ${HEADERS_M680X}
     ${HEADERS_EVM}
+    ${HEADERS_MOS65XX}
     )
 
 include_directories("${PROJECT_SOURCE_DIR}/include")
@@ -435,14 +514,14 @@ endif ()
 # Force static runtime libraries
 if (CAPSTONE_BUILD_STATIC_RUNTIME)
     FOREACH(flag
-       CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
-       CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
-       CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
-       CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
-       if (MSVC)
-           STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
-           SET("${flag}" "${${flag}} /EHsc")
-       endif (MSVC)
+    CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
+    CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
+    CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
+    CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
+    if (MSVC)
+        STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
+        SET("${flag}" "${${flag}} /EHsc")
+    endif (MSVC)
     ENDFOREACH()
 endif ()
 
@@ -455,13 +534,13 @@ if (CAPSTONE_BUILD_SHARED)
         set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
     else()
         set_target_properties(capstone-shared PROPERTIES
-           VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
-           SOVERSION ${VERSION_MAJOR})
+        VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
+        SOVERSION ${VERSION_MAJOR})
     endif ()
 
     if(NOT DEFINED default-target)      # honor `capstone-static` for tests first.
-       set(default-target capstone-shared)
-       add_definitions(-DCAPSTONE_SHARED)
+        set(default-target capstone-shared)
+        add_definitions(-DCAPSTONE_SHARED)
     endif ()
 endif ()
 
@@ -479,6 +558,9 @@ if (CAPSTONE_BUILD_TESTS)
         target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
         add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN})
     endif()
+    # fuzz target built with the tests
+    add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c)
+    target_link_libraries(fuzz_disasm ${default-target})
 endif ()
 
 source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
@@ -494,6 +576,7 @@ source_group("Source\\M68K" FILES ${SOURCES_M68K})
 source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X})
 source_group("Source\\M680X" FILES ${SOURCES_M680X})
 source_group("Source\\EVM" FILES ${SOURCES_EVM})
+source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
 
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -509,35 +592,29 @@ source_group("Include\\M68K" FILES ${HEADERS_M68K})
 source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X})
 source_group("Include\\M680X" FILES ${HEADERS_MC680X})
 source_group("Include\\EVM" FILES ${HEADERS_EVM})
+source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
 
 ### test library 64bit routine:
-get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS)
-
-if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE")
-    set(LIBSUFFIX 64)
-else()
-    set(LIBSUFFIX "")
-endif()
-
-set(INSTALL_LIB_DIR     lib${LIBSUFFIX} CACHE PATH "Installation directory for libraries")
-mark_as_advanced(INSTALL_LIB_DIR)
+include("GNUInstallDirs")
 
 ## installation
-install(FILES ${HEADERS_COMMON} DESTINATION include/capstone)
-configure_file(capstone.pc.in capstone.pc @ONLY)
+if (CAPSTONE_INSTALL)
+    install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone)
+endif ()
+configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY)
 
-if (CAPSTONE_BUILD_STATIC)
+if (CAPSTONE_BUILD_STATIC AND CAPSTONE_INSTALL)
     install(TARGETS capstone-static
             RUNTIME DESTINATION bin
-            LIBRARY DESTINATION ${INSTALL_LIB_DIR}
-            ARCHIVE DESTINATION ${INSTALL_LIB_DIR})
+            LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
+            ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
 endif ()
 
-if (CAPSTONE_BUILD_SHARED)
+if (CAPSTONE_BUILD_SHARED AND CAPSTONE_INSTALL)
     install(TARGETS capstone-shared
             RUNTIME DESTINATION bin
-            LIBRARY DESTINATION ${INSTALL_LIB_DIR}
-            ARCHIVE DESTINATION ${INSTALL_LIB_DIR})
+            LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
+            ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
 endif ()
 
 if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL)
@@ -545,6 +622,8 @@ FILE(GLOB CSTOOL_SRC cstool/*.c)
 add_executable(cstool ${CSTOOL_SRC})
 target_link_libraries(cstool ${default-target})
 
-install(TARGETS cstool DESTINATION bin)
-install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION lib/pkgconfig)
+if (CAPSTONE_INSTALL)
+    install(TARGETS cstool DESTINATION bin)
+    install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig)
+endif ()
 endif ()
index 56aecad762c1bf2382df6e6121cb68ff6efc0763..a4f4a6b13017b172052aa69f8a3eb834e06c277c 100644 (file)
@@ -17,16 +17,15 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
 (0) Tailor Capstone to your need.
 
-  Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
-  Sparc, SystemZ, XCore, X86, M680X, TMS320C64x & EVM), if you just need several
+  Out of all archtitectures supported by Capstone, if you just need several
   selected archs, choose the ones you want to compile in by editing "config.mk"
   before going to next steps.
 
-  By default, all 12 architectures are compiled.
+  By default, all architectures are compiled.
 
   The other way of customize Capstone without having to edit config.mk is to
   pass the desired options on the commandline to ./make.sh. Currently,
-  Capstone supports 5 options, as followings.
+  Capstone supports 7 options, as followings.
 
   - CAPSTONE_ARCHS: specify list of architectures to compiled in.
   - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
@@ -56,11 +55,11 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
   - To compile for current platform, run:
 
-               $ ./make.sh
+        $ ./make.sh
 
   - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
 
-               $ ./make.sh nix32
+        $ ./make.sh nix32
 
 
 
@@ -68,11 +67,11 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
   To install Capstone, run:
 
-       $ sudo ./make.sh install
+    $ sudo ./make.sh install
 
-       For FreeBSD/OpenBSD, where sudo is unavailable, run:
+    For FreeBSD/OpenBSD, where sudo is unavailable, run:
 
-               $ su; ./make.sh install
+        $ su; ./make.sh install
 
   Users are then required to enter root password to copy Capstone into machine
   system directories.
@@ -83,22 +82,23 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
   NOTE: The core framework installed by "./make.sh install" consist of
   following files:
 
-       /usr/include/capstone/capstone.h
-       /usr/include/capstone/x86.h
-       /usr/include/capstone/arm.h
-       /usr/include/capstone/arm64.h
-       /usr/include/capstone/evm.h
-       /usr/include/capstone/m68k.h
-       /usr/include/capstone/m680x.h
-       /usr/include/capstone/mips.h
-       /usr/include/capstone/ppc.h
-       /usr/include/capstone/sparc.h
-       /usr/include/capstone/systemz.h
-       /usr/include/capstone/tms320c64x.h
-       /usr/include/capstone/xcore.h
-       /usr/include/capstone/platform.h
-       /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
-       /usr/lib/libcapstone.a
+    /usr/include/capstone/arm.h
+    /usr/include/capstone/arm64.h
+    /usr/include/capstone/capstone.h
+    /usr/include/capstone/evm.h
+    /usr/include/capstone/m680x.h
+    /usr/include/capstone/m68k.h
+    /usr/include/capstone/mips.h
+    /usr/include/capstone/mos65xx.h
+    /usr/include/capstone/platform.h
+    /usr/include/capstone/ppc.h
+    /usr/include/capstone/sparc.h
+    /usr/include/capstone/systemz.h
+    /usr/include/capstone/tms320c64x.h
+    /usr/include/capstone/x86.h
+    /usr/include/capstone/xcore.h
+    /usr/lib/libcapstone.a
+    /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
 
 
 
@@ -107,13 +107,13 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
   To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
   for 64-bit binaries) are required.
 
-       - To cross-compile Windows 32-bit binary, simply run:
+    - To cross-compile Windows 32-bit binary, simply run:
 
-               $ ./make.sh cross-win32
+        $ ./make.sh cross-win32
 
-       - To cross-compile Windows 64-bit binary, run:
+    - To cross-compile Windows 64-bit binary, run:
 
-               $ ./make.sh cross-win64
+        $ ./make.sh cross-win64
 
   Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
   be used on Windows machine.
@@ -122,19 +122,19 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
 (4) Cross-compile for iOS from Mac OSX.
 
-  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. 
+  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required.
 
-       - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
-               $ ./make.sh ios_armv7
+    - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
+        $ ./make.sh ios_armv7
 
-       - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
-               $ ./make.sh ios_armv7s
+    - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
+        $ ./make.sh ios_armv7s
 
-       - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
-               $ ./make.sh ios_arm64
+    - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
+        $ ./make.sh ios_arm64
 
-       - To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
-               $ ./make.sh ios
+    - To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
+        $ ./make.sh ios
 
   Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
   be used on iOS devices.
@@ -146,9 +146,9 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
   To cross-compile for Android (smartphone/tablet), Android NDK is required.
   NOTE: Only ARM and ARM64 are currently supported.
 
-       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
+    $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
   or
-       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
+    $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
 
   Resulted files libcapstone.so, libcapstone.a & tests/test* can then
   be used on Android devices.
@@ -174,19 +174,19 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
 (7) By default, "cc" (default C compiler on the system) is used as compiler.
 
-       - To use "clang" compiler instead, run the command below:
+    - To use "clang" compiler instead, run the command below:
 
-               $ ./make.sh clang
+        $ ./make.sh clang
 
-       - To use "gcc" compiler instead, run:
+    - To use "gcc" compiler instead, run:
 
-               $ ./make.sh gcc
+        $ ./make.sh gcc
 
 
 
 (8) To uninstall Capstone, run the command below:
 
-               $ sudo ./make.sh uninstall
+        $ sudo ./make.sh uninstall
 
 
 
index 6b35d8d8e46a024c37532ab26e61c55c700dfb16..e89d0d83e88a79735c3970f163359a085c96da69 100644 (file)
@@ -16,8 +16,7 @@ Get CMake for free from http://www.cmake.org.
 
 (0) Tailor Capstone to your need.
 
-  Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
-  Sparc, SystemZ, X86, XCore, M680X, TMS320C64x & EVM), if you just need several selected archs,
+  Out of archtitectures supported by Capstone, if you just need several selected archs,
   run "cmake" with the unwanted archs disabled (set to 0) as followings.
 
   - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
@@ -25,16 +24,19 @@ Get CMake for free from http://www.cmake.org.
   - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
   - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
   - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
+  - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX.
   - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
   - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
   - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
   - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
   - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
-  - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
-  - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
-  - CAPSTONE_X86_EVM: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM.
+  - CAPSTONE_TMS320C64X_SUPPORT: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
+  - CAPSTONE_EVM_SUPPORT: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM.
+  - CAPSTONE_ARCHITECUTRE_DEFAULT: Whether architectures are enabled by default.
+      Set this of OFF with -DCAPSTONE_ARCHITECUTRE_DEFAULT=OFF to dissable all architectures by default.
+      You can then enable them again with one of the CAPSTONE_<ARCH>_SUPPORT options.
 
-  By default, all 10 architectures are compiled in.
+  By default, all architectures are compiled in.
 
 
   Besides, Capstone also allows some more customization via following macros.
@@ -56,6 +58,17 @@ Get CMake for free from http://www.cmake.org.
 (1) CMake allows you to generate different generators to build Capstone. Below is
     some examples on how to build Capstone on Windows with CMake.
 
+  (*) You can let CMake select a generator for you. Do:
+
+      mkdir build
+      cd build
+      cmake ..
+
+    This last command is also where you can pass additional CMake configuration flags
+    using `-D<key>=<value>`. Then to build use:
+
+      cmake --build . --config Release
+
 
   (*) To build Capstone using Nmake of Windows SDK, do:
 
@@ -83,3 +96,19 @@ Get CMake for free from http://www.cmake.org.
 (2) You can make sure the prior steps successfully worked by launching one of the
   testing binary (test*.exe).
 
+(3) You can also enable just one specific architecture by passing the architecture name
+  to either the cmake.sh or nmake.bat scripts. e.g.:
+
+    ../cmake.sh x86
+
+  Will just target the x86 architecture. The list of available architectures is: ARM,
+  ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX.
+
+(4) You can also create an installation image with cmake, by using the 'install' target.
+  Use:
+
+    cmake --build . --config Release --target install
+
+  This will normally install an image in a default location (`C:\Program Files` on Windows),
+  so it's good to explicitly set this location when configuring CMake. Use: `-DCMAKE_INSTALL_PREFIX=image`
+  for instance, to put the installation in the 'image' subdirectory of the build directory.
index 24705ed36335153fb144b1e1637dfcd85ac3d7d2..b2d9bdd26cdde36495507e854807473286c6aad1 100644 (file)
@@ -23,8 +23,8 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
   the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
   then directly editing the projects "capstone_static" & "capstone_dll" for static
-  and dynamic libraries, respectively. This must be done before going to the
-  next steps.
+  and dynamic libraries, respectively. This must be done before going to the next
+  steps.
 
   In VisualStudio interface, modify the preprocessor definitions via
   "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor"
@@ -34,7 +34,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
   - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
   - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
-  - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support.
+  - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.
   - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
   - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
   - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
@@ -106,3 +106,17 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
 
       >sc delete test_winkernel
       >bcdedit /deletevalue testsigning
+      
+      
+      
+(3) Installing and building capstone via vcpkg
+  
+  You can download and install capstone using the vcpkg(https://github.com/Microsoft/vcpkg) dependency manager:
+
+    git clone https://github.com/Microsoft/vcpkg.git
+    cd vcpkg
+    ./bootstrap-vcpkg.sh
+    ./vcpkg integrate install
+    vcpkg install capstone
+
+  The capstone port in vcpkg is kept up to date by Microsoft team members and community contributors. If the version is out of date, please create an issue or pull request on the vcpkg repository(https://github.com/Microsoft/vcpkg). 
\ No newline at end of file
index 5418cc675368411f0664bc60c84cb264f5e71506..1329e01f6fd6d20334a56d0e433ff6d7459b1b60 100644 (file)
@@ -3,17 +3,17 @@ This file credits all the contributors of the Capstone engine project.
 Key developers
 ==============
 1. Nguyen Anh Quynh <aquynh -at- gmail.com>
-       - Core engine
-       - Bindings: Python, Ruby, OCaml, Java, C#
+    - Core engine
+    - Bindings: Python, Ruby, OCaml, Java, C#
 
 2. Tan Sheng Di <shengdi -at- coseinc.com>
-       - Bindings: Ruby
+    - Bindings: Ruby
 
 3. Ben Nagy <ben -at- coseinc.com>
-       - Bindings: Ruby, Go
+    - Bindings: Ruby, Go
 
 4. Dang Hoang Vu <dang.hvu -at- gmail.com>
-       - Bindings: Java
+    - Bindings: Java
 
 
 Beta testers (in random order)
@@ -49,12 +49,21 @@ Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
 Daniel Pistelli: Cmake support.
 Peter Hlavaty: integrate Capstone for Windows kernel drivers.
 Guillaume Jeanne: Ocaml binding.
-Martin Tofall, Obsidium Software: Optimize X86 performance & size.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
 David Martínez Moreno & Hilko Bengen: Debian package.
 Félix Cloutier: Xcode project.
 Benoit Lecocq: OpenBSD package.
 Christophe Avoinne (Hlide): Improve memory management for better performance.
 Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Tang Yuhang: cstool.
+Andrew Dutcher: better Python setup.
+Ruben Boonen: PowerShell binding.
+David Zimmer: VB6 binding.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
 Bui Dinh Cuong: Explicit registers accessed for Arm64.
 Vincent Bénony: Explicit registers accessed for X86.
 Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
@@ -66,4 +75,9 @@ Satoshi Tanda: Support Windows kernel driver.
 Koutheir Attouchi: Support for Windows CE.
 Fotis Loukos: TMS320C64x architecture.
 Wolfgang Schwotzer: M680X architecture.
-
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Stephen Eckels (stevemk14ebr): x86 encoding features
+Sebastian Macke: MOS65XX architecture
+Ilya Leoshkevich: SystemZ architecture improvements.
+Do Minh Tuan: Regression testing tool (cstest)
+Kevin Foo (chfl4gs): PyPI github actions workflow.
index 1094cffe0b5f75bd335e0fca477b2ce41e29adfe..62c4c4952c04b27dad6e76557b1584fed4b508cc 100644 (file)
 This file details the changelog of Capstone.
 
+---------------------------------
+Version 4.0.1: January 10th, 2019
+
+
+[ Core ]
+
+- Fix some issues for packaging (Debian, Gentoo).
+- Better support for building with Mingw.
+- cstool has new option -s to turn on skipdata mode.
+- cstool -v now report build settings of the core.
+- Add suite/capstone_get_setup.c so users can integrate with their own code
+  to retrieve Capstone settings at build time.
+
+
 [ Arm ]
 
-- Fix a bug where Arm.Operand is wrongly calculated for the second and
-  following operands
-- Fix a bug where Arm.OpInfo.memBarrier and Arm.OpInfo.op is wrongly
-  calculated
+- Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back again (see #1317)
+- Remove ARM_REG_PC group for BX instruction.
 
-[ Bindings ]
 
-- Java; add Capstone.strerror() and CsInsn.regsAccess().
+[ X86 ]
+
+- Fix: endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64  (#1129)
+
+
+[ M680X ]
+
+- Fix some issues reported by clang-analyzer (#1329).
+
+
+[ Python ]
+
+- Fix skipdata setup.
+- Add getter/setter for skipdata_mnem, skipdata_callback.
+
+
+---------------------------------
+Version 4.0: December 18th, 2018
+
+
+[ Core ]
+
+- New APIs: cs_regs_access()
+- Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM.
+- Various updates & bugfixes for all architectures.
+- Add 4 new architectures: EVM, M68K, M680X & TMS320C64x.
+- Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE.
+- Add new error types: CS_ERR_X86_MASM.
+
+
+[ X86 ]
+
+- Add XOP code condition type in x86_xop_cc.
+- Add some info on encoding to cs_x86 in cs_x86_encoding.
+- Add register flags update in cs_x86.{eflags, fpu_flags}
+- Change cs_x86.disp type from int32_t to int64_t.
+- Add new groups: X86_GRP_VM & X86_GRP_FPU.
+- Lots of new instructions (AVX)
+
+
+[ ARM64 ]
+
+- Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS.
+
+
+[ Mips ]
+
+- Add mode CS_MODE_MIPS2.
+
+
+[ PPC ]
+
+- Change cs_ppc_op.imm type from int32_t to int64_t.
+- Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX.
+- Lots of new instructions (QPX among them)
+
+
+[ Sparc ]
+
+- Change cs_sparc_op.imm type from int32_t to int64_t.
+
+
+[ Binding ]
+
+- New bindings: PowerShell & VB6
+
+
+---------------------------------
+Version 3.0.5: July 18th, 2018
+
+
+[ Core ]
+
+- Fix the include path for Android builds when building cstool.
+- Add posibility to disable universal build for Mac OS.
+- cstool: Separate instruction bytes by spaces.
+- Fix code path of pkg-config in Cmake.
+- Update XCode project for XCode 9.1.
+- Add Cortex-M support to cstool.
+- Cmake forces to be build using MT with MSVC.
+- Better support for Mac OS kernel.
+
+
+[ X86 ]
+
+- Fix some issues in handling EVEX & VEX3 instructions.
+- Fix immediate operand for AND instruction in ATT mode.
+- Fix ATT syntax when imm operand is 0.
+- Better handle XACQUIRE/XRELEASE.
+- Fix imm operand of RETF.
+
+
+[ ARM ]
+
+- Fix an integer overlow bug.
+
+
+[ ARM64 ]
+
+- Bug fix for incorrect operand type in certain load/store instructions.
+
+
+[ Mips ]
+
+- Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32
+
+
+[ PPC ]
+
+- Fix endian check.
+
+
+[ Sparc ]
+
+- Fix an integer overlow bug.
+
+
+[ SystemZ ]
+
+- Fix an integer overlow bug.
+
+
+[ Python binding ]
+
+- Raise error on accessing irrelevant data fields if skipdata & detail modes are enable.
+
+
+---------------------------------
+Version 3.0.5-rc3: July 31st, 2017
+
+
+[ Core ]
+
+- Fix compilation for MacOS kernel extension
+- cstool to support armbe and arm64be modes
+- Add nmake.bat for Windows build
+- Fix an integer overflow for Windows kernel driver
+- Support to embedded Capstone into MacOS kernel
+- cstool: fix mips64 mode
+- Fix a compiling error in MS Visual Studio 2015
+- Install pkgconfig file with CMake build
+- Fix SOVERSION property of CMake build
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+- Fix MingW build
+- Better handle CMake installation for Linux 64bit
+
+
+[ X86 ]
+
+- Support BND prefix of Intel MPX extension
+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66
+- LOCK NOP is a valid instruction
+- Fix ATT syntax for instruction with zero offset segment register
+- LES/LDS are invalid in 64bit mode
+- Fix number of operands for some MOV instructions
+
+
+[ ARM ]
+
+- Fix POP reg to update SP register
+- Update flags for UADD8 instruction
+
+
+[ ARM64 ]
+
+- Better performance with new lookup table
+- Handle system registers added in ARMv8.1/2
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ Visual Basic binding ]
+
+- New binding
+
+---------------------------------
+Version 3.0.5-rc2: March 2nd, 2017
+
+
+[ Core ]
+
+- Fix build for Visual Studio 2012
+- Fix X86_REL_ADDR macro
+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA
+- Better support for embedding Capstone into Windows kernel drivers
+- Support to embedded Capstone into MacOS kernel
+- Support MacOS 10.11 and up
+- Better support for Cygwin
+- Support build packages for FreeBSD & DragonflyBSD
+- Add a command-line tool "cstool"
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+
+
+[ X86 ]
+
+- Some random 16-bit code can be handled wrongly.
+- Remove abundant operand type X86_OP_FP
+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL
+- Add X86_REG_EFLAGS for STC and STD
+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
+- Rename registers ST0-ST7 to be consistent with asm output
+
+
+[ ARM ]
+
+- Properly handle IT instruction
+- Fix LDRSB
+- Fix writeback for LDR
+- Fix Thumb BigEndian setup
+
+
+[ ARM64 ]
+
+- Fix arith extender
+- Fix writeback for LDR
+- Rename enum arm64_mrs_reg to arm64_sysreg
+
+
+[ PowerPC ]
+
+- Print 0 offset for memory operand
+
+
+[ Sparc ]
+
+- Fix POPC instruction
+
+
+[ Python binding ]
+
+- Better PyPy support
+- Add __version__
+- Better support for Python 3
+- Fix CS_SKIPDATA_CALLBACK prototype
+- Cast skipdata function inside binding to simplify the API
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ PowerShell ]
+
+- New binding
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+  was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+  GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+  "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
 
 ---------------------------------
 Version 3.0.2: March 11th, 2015
@@ -244,14 +588,14 @@ Version 2.1: March 5th, 2014
 
 - Update all 5 architectures to fix bugs.
 - PowerPC:
-       - New instructions: FMR & MSYNC.
+    - New instructions: FMR & MSYNC.
 - Mips:
-       - New instruction: DLSA
+    - New instruction: DLSA
 - X86:
-       - Properly handle AVX-512 instructions.
-       - New instructions: PSETPM, SALC, INT1, GETSEC.
-       - Fix some memory leaking issues in case of prefixed instructions such
-         as LOCK, REP, REPNE.
+    - Properly handle AVX-512 instructions.
+    - New instructions: PSETPM, SALC, INT1, GETSEC.
+    - Fix some memory leaking issues in case of prefixed instructions such
+      as LOCK, REP, REPNE.
 
 
 [ Python binding ]
@@ -282,7 +626,7 @@ Version 2.1: March 5th, 2014
 
 - make.sh now can uninstall the core engine. This is done with:
 
-       $ sudo ./make.sh uninstall
+    $ sudo ./make.sh uninstall
 
 ----------------------------------
 Version 2.0: January 22nd, 2014
@@ -320,7 +664,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
 - Arm
      - Support Big-Endian mode (besides Little-Endian mode).
      - Support friendly register, so instead of output sub "r12,r11,0x14",
-        we have "sub ip,fp,0x14".
+     we have "sub ip,fp,0x14".
 - Arm64: support Big-Endian mode (besides Little-Endian mode).
 - PowerPC: newly added.
 - Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
index e641c68b3c9407ee8cdb4cf3cc624e4e479a0c06..2714eb89b7dbb5966d461396aed3747ec46089ed 100644 (file)
@@ -1,16 +1,21 @@
-Capstone source is organized as followings.
+Code structure
+--------------
 
+Capstone source is organized as followings.
 
 .                   <- core engine + README + COMPILE.TXT etc
 ├── arch            <- code handling disasm engine for each arch
 │   ├── AArch64     <- ARM64 (aka ARMv8) engine
 │   ├── ARM         <- ARM engine
+│   ├── EVM         <- Ethereum engine
 │   ├── M680X       <- M680X engine
 │   ├── M68K        <- M68K engine
 │   ├── Mips        <- Mips engine
+│   ├── MOS65XX     <- MOS65XX engine
 │   ├── PowerPC     <- PowerPC engine
 │   ├── Sparc       <- Sparc engine
 │   ├── SystemZ     <- SystemZ engine
+│   ├── TMS320C64x  <- TMS320C64x engine
 │   ├── X86         <- X86 engine
 │   └── XCore       <- XCore engine
 ├── bindings        <- all bindings are under this dir
@@ -34,15 +39,64 @@ Follow instructions in COMPILE.TXT for how to compile and run test code.
 Note: if you find some strange bugs, it is recommended to firstly clean
 the code and try to recompile/reinstall again. This can be done with:
 
-       $ ./make.sh
-       $ sudo ./make.sh install
+    $ ./make.sh
+    $ sudo ./make.sh install
 
 Then test Capstone with cstool, for example:
 
-       $ cstool x32 "90 91"
+    $ cstool x32 "90 91"
 
 At the same time, for Java/Ocaml/Python bindings, be sure to always use
 the bindings coming with the core to avoid potential incompatibility issue
 with older versions.
 See bindings/<language>/README for detail instructions on how to compile &
 install the bindings.
+
+
+Coding style
+------------
+- C code follows Linux kernel coding style, using tabs for indentation.
+- Python code uses 4 spaces for indentation.
+
+
+Adding an architecture
+----------------------
+
+Obviously, you first need to write all the logic and put it in a new directory arch/newarch
+Then, you have to modify other files.
+(You can look for one architecture such as EVM in these files to get what you need to do)
+
+Integrate:
+- cs.c
+- cstool/cstool.c
+- cstool/cstool_newarch.c: print the architecture specific details
+- include/capstone/capstone.h
+- include/capstone/newarch.h: create this file to export all specifics about the new architecture
+
+Compile:
+- CMakeLists.txt
+- Makefile
+- config.mk
+
+Tests:
+- tests/Makefile
+- tests/test_basic.c
+- tests/test_detail.c
+- tests/test_iter.c
+- tests/test_newarch.c
+- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms
+
+Bindings:
+- bindings/Makefile
+- bindings/const_generator.py: add the header file and the architecture
+- bindings/python/Makefile
+- bindings/python/capstone/__init__.py
+- bindings/python/capstone/newarch.py: define the python structures
+- bindings/python/capstone/newarch_const.py: generate this file
+- bindings/python/test_newarch.py: create a basic decoding test
+- bindings/python/test_all.py
+
+Docs:
+- README.md
+- HACK.txt
+- CREDITS.txt: add your name
index da4140cab731a1efcb9b29afe54d78cc045fdfc1..acf2e09288261bd2255a1d4b53daeddd90208511 100644 (file)
 /// Utility function to decode a ULEB128 value.
 static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
 {
-       const uint8_t *orig_p = p;
-       uint64_t Value = 0;
-       unsigned Shift = 0;
-       do {
-               Value += (*p & 0x7f) << Shift;
-               Shift += 7;
-       } while (*p++ >= 128);
-       if (n)
-               *n = (unsigned)(p - orig_p);
-       return Value;
+    const uint8_t *orig_p = p;
+    uint64_t Value = 0;
+    unsigned Shift = 0;
+    do {
+        Value += (uint64_t)(*p & 0x7f) << Shift;
+        Shift += 7;
+    } while (*p++ >= 128);
+    if (n)
+        *n = (unsigned)(p - orig_p);
+    return Value;
 }
 
 #endif  // LLVM_SYSTEM_LEB128_H
index 35d8e630604993bc5ab54a288eb40103d599ea20..1c3ea767e25bdd249a319813247ee97af70d6527 100644 (file)
@@ -5,9 +5,9 @@
 #define CS_MCDISASSEMBLER_H
 
 typedef enum DecodeStatus {
-       MCDisassembler_Fail = 0,
-       MCDisassembler_SoftFail = 1,
-       MCDisassembler_Success = 3,
+    MCDisassembler_Fail = 0,
+    MCDisassembler_SoftFail = 1,
+    MCDisassembler_Success = 3,
 } DecodeStatus;
 
 #endif
index 27ac115ed07165fc4e304f98d4e51959922ea440..e0263841d60075243d89967d969d7349d11e2ee4 100644 (file)
 
 // Disassembler state machine opcodes.
 enum DecoderOps {
-       MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
-       MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
-       MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
-                                                         //                uleb128 Val, uint16_t NumToSkip)
-       MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
-       MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
-       MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
-       MCD_OPC_Fail              // OPC_Fail()
+    MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
+    MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
+    MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
+                              //                uleb128 Val, uint16_t NumToSkip)
+    MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
+    MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+    MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
+    MCD_OPC_Fail              // OPC_Fail()
 };
 
 #endif
index cc062d0044620deeb9ae5d537a22c53707add95e..bc9b170135ea6dfa521ba2fa2c672cdf7e07b440 100644 (file)
@@ -2,6 +2,7 @@
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
 
 #if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
 #include <libkern/libkern.h>
 #else
 #include <stdio.h>
 
 void MCInst_Init(MCInst *inst)
 {
-       inst->Opcode = 0;
-       inst->OpcodePub = 0;
-       inst->size = 0;
-       inst->has_imm = false;
-       inst->op1_size = 0;
-       inst->writeback = false;
-       inst->ac_idx = 0;
-       inst->popcode_adjust = 0;
-       inst->assembly[0] = '\0';
+    unsigned int i;
+
+    for (i = 0; i < 48; i++) {
+        inst->Operands[i].Kind = kInvalid;
+        inst->Operands[i].ImmVal = 0;
+    }
+
+    inst->Opcode = 0;
+    inst->OpcodePub = 0;
+    inst->size = 0;
+    inst->has_imm = false;
+    inst->op1_size = 0;
+    inst->writeback = false;
+    inst->ac_idx = 0;
+    inst->popcode_adjust = 0;
+    inst->assembly[0] = '\0';
 }
 
 void MCInst_clear(MCInst *inst)
 {
-       inst->size = 0;
+    inst->size = 0;
 }
 
 // do not free @Op
 void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
 {
-       int i;
+    int i;
 
-       for(i = inst->size; i > index; i--)
-               //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
-               inst->Operands[i] = inst->Operands[i-1];
+    for(i = inst->size; i > index; i--)
+        //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+        inst->Operands[i] = inst->Operands[i-1];
 
-       inst->Operands[index] = *Op;
-       inst->size++;
+    inst->Operands[index] = *Op;
+    inst->size++;
 }
 
 void MCInst_setOpcode(MCInst *inst, unsigned Op)
 {
-       inst->Opcode = Op;
+    inst->Opcode = Op;
 }
 
 void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
 {
-       inst->OpcodePub = Op;
+    inst->OpcodePub = Op;
 }
 
 unsigned MCInst_getOpcode(const MCInst *inst)
 {
-       return inst->Opcode;
+    return inst->Opcode;
 }
 
 unsigned MCInst_getOpcodePub(const MCInst *inst)
 {
-       return inst->OpcodePub;
+    return inst->OpcodePub;
 }
 
 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
 {
-       return &inst->Operands[i];
+    return &inst->Operands[i];
 }
 
 unsigned MCInst_getNumOperands(const MCInst *inst)
 {
-       return inst->size;
+    return inst->size;
 }
 
 // This addOperand2 function doesnt free Op
 void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
 {
-       inst->Operands[inst->size] = *Op;
+    inst->Operands[inst->size] = *Op;
 
-       inst->size++;
-}
-
-void MCOperand_Init(MCOperand *op)
-{
-       op->Kind = kInvalid;
-       op->FPImmVal = 0.0;
+    inst->size++;
 }
 
 bool MCOperand_isValid(const MCOperand *op)
 {
-       return op->Kind != kInvalid;
+    return op->Kind != kInvalid;
 }
 
 bool MCOperand_isReg(const MCOperand *op)
 {
-       return op->Kind == kRegister;
+    return op->Kind == kRegister;
 }
 
 bool MCOperand_isImm(const MCOperand *op)
 {
-       return op->Kind == kImmediate;
+    return op->Kind == kImmediate;
 }
 
 bool MCOperand_isFPImm(const MCOperand *op)
 {
-       return op->Kind == kFPImmediate;
+    return op->Kind == kFPImmediate;
 }
 
 /// getReg - Returns the register number.
 unsigned MCOperand_getReg(const MCOperand *op)
 {
-       return op->RegVal;
+    return op->RegVal;
 }
 
 /// setReg - Set the register number.
 void MCOperand_setReg(MCOperand *op, unsigned Reg)
 {
-       op->RegVal = Reg;
+    op->RegVal = Reg;
 }
 
 int64_t MCOperand_getImm(MCOperand *op)
 {
-       return op->ImmVal;
+    return op->ImmVal;
 }
 
 void MCOperand_setImm(MCOperand *op, int64_t Val)
 {
-       op->ImmVal = Val;
+    op->ImmVal = Val;
 }
 
 double MCOperand_getFPImm(const MCOperand *op)
 {
-       return op->FPImmVal;
+    return op->FPImmVal;
 }
 
 void MCOperand_setFPImm(MCOperand *op, double Val)
 {
-       op->FPImmVal = Val;
+    op->FPImmVal = Val;
 }
 
 MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
 {
-       MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+    MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
 
-       op->Kind = kRegister;
-       op->RegVal = Reg;
+    op->Kind = kRegister;
+    op->RegVal = Reg;
 
-       return op;
+    return op;
 }
 
 void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
 {
-       MCOperand *op = &(mcInst->Operands[mcInst->size]);
-       mcInst->size++;
+    MCOperand *op = &(mcInst->Operands[mcInst->size]);
+    mcInst->size++;
 
-       op->Kind = kRegister;
-       op->RegVal = Reg;
+    op->Kind = kRegister;
+    op->RegVal = Reg;
 }
 
 MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
 {
-       MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+    MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
 
-       op->Kind = kImmediate;
-       op->ImmVal = Val;
+    op->Kind = kImmediate;
+    op->ImmVal = Val;
 
-       return op;
+    return op;
 }
 
 void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
 {
-       MCOperand *op = &(mcInst->Operands[mcInst->size]);
-       mcInst->size++;
+    MCOperand *op = &(mcInst->Operands[mcInst->size]);
+    mcInst->size++;
 
-       op->Kind = kImmediate;
-       op->ImmVal = Val;
+    op->Kind = kImmediate;
+    op->ImmVal = Val;
 }
index 6a707419d21db4c46714c5f205675d7f863c97fd..db1c0c8952656433196b3eaa2db19e5ebd702f3a 100644 (file)
@@ -28,19 +28,19 @@ typedef struct MCOperand MCOperand;
 /// MCOperand - Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
 struct MCOperand {
-       enum {
-               kInvalid = 0,                 ///< Uninitialized.
-               kRegister,                ///< Register operand.
-               kImmediate,               ///< Immediate operand.
-               kFPImmediate,             ///< Floating-point immediate operand.
-       } MachineOperandType;
-       unsigned char Kind;
-
-       union {
-               unsigned RegVal;
-               int64_t ImmVal;
-               double FPImmVal;
-       };
+    enum {
+        kInvalid = 0,                 ///< Uninitialized.
+        kRegister,                ///< Register operand.
+        kImmediate,               ///< Immediate operand.
+        kFPImmediate,             ///< Floating-point immediate operand.
+    } MachineOperandType;
+    unsigned char Kind;
+
+    union {
+        unsigned RegVal;
+        int64_t ImmVal;
+        double FPImmVal;
+    };
 };
 
 bool MCOperand_isValid(const MCOperand *op);
@@ -53,8 +53,6 @@ bool MCOperand_isFPImm(const MCOperand *op);
 
 bool MCOperand_isInst(const MCOperand *op);
 
-void MCInst_clear(MCInst *m);
-
 /// getReg - Returns the register number.
 unsigned MCOperand_getReg(const MCOperand *op);
 
@@ -88,28 +86,28 @@ MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
 /// MCInst - Instances of this class represent a single low-level machine
 /// instruction.
 struct MCInst {
-       unsigned OpcodePub;
-       uint8_t size;   // number of operands
-       bool has_imm;   // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
-       uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
-       unsigned Opcode;
-       MCOperand Operands[48];
-       cs_insn *flat_insn;     // insn to be exposed to public
-       uint64_t address;       // address of this insn
-       cs_struct *csh; // save the main csh
-       uint8_t x86opsize;      // opsize for [mem] operand
-
-       // (Optional) instruction prefix, which can be up to 4 bytes.
-       // A prefix byte gets value 0 when irrelevant.
-       // This is copied from cs_x86 struct
-       uint8_t x86_prefix[4];
-       uint8_t imm_size;       // immediate size for X86_OP_IMM operand
-       bool writeback; // writeback for ARM
-       // operand access index for list of registers sharing the same access right (for ARM)
-       uint8_t ac_idx;
-       uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
-       char assembly[8];       // for special instruction, so that we dont need printer
-       unsigned char evm_data[32];     // for EVM PUSH operand
+    unsigned OpcodePub;
+    uint8_t size;    // number of operands
+    bool has_imm;    // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
+    uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
+    unsigned Opcode;
+    MCOperand Operands[48];
+    cs_insn *flat_insn;    // insn to be exposed to public
+    uint64_t address;    // address of this insn
+    cs_struct *csh;    // save the main csh
+    uint8_t x86opsize;    // opsize for [mem] operand
+
+    // (Optional) instruction prefix, which can be up to 4 bytes.
+    // A prefix byte gets value 0 when irrelevant.
+    // This is copied from cs_x86 struct
+    uint8_t x86_prefix[4];
+    uint8_t imm_size;    // immediate size for X86_OP_IMM operand
+    bool writeback;    // writeback for ARM
+    // operand access index for list of registers sharing the same access right (for ARM)
+    uint8_t ac_idx;
+    uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
+    char assembly[8];    // for special instruction, so that we dont need printer
+    unsigned char evm_data[32];    // for EVM PUSH operand
 };
 
 void MCInst_Init(MCInst *inst);
index 8186e1ab0a58e80324b7cca441753678e1386320..4e06de1e9ed86cf3a9bfd72b6390ad6556e387c9 100644 (file)
@@ -5,14 +5,14 @@
 
 /// isPredicate - Set if this is one of the operands that made up of
 /// the predicate operand that controls an isPredicable() instruction.
-bool MCOperandInfo_isPredicate(MCOperandInfo *m)
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
 {
-       return m->Flags & (1 << MCOI_Predicate);
+    return m->Flags & (1 << MCOI_Predicate);
 }
 
 /// isOptionalDef - Set if this operand is a optional def.
 ///
-bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
 {
-       return m->Flags & (1 << MCOI_OptionalDef);
+    return m->Flags & (1 << MCOI_OptionalDef);
 }
index 275ae77f8caa9f908b1aa2e3b3b0484b2ab6960e..786b5720e942bbe944c6b6a971be147dd5b7937e 100644 (file)
 
 // Operand constraints
 enum MCOI_OperandConstraint {
-       MCOI_TIED_TO = 0,    // Must be allocated the same register as.
-       MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+    MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+    MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
 };
 
 /// OperandFlags - These are flags set on operands, but should be considered
 /// private, all access should go through the MCOperandInfo accessors.
 /// See the accessors for a description of what these are.
 enum MCOI_OperandFlags {
-       MCOI_LookupPtrRegClass = 0,
-       MCOI_Predicate,
-       MCOI_OptionalDef
+    MCOI_LookupPtrRegClass = 0,
+    MCOI_Predicate,
+    MCOI_OptionalDef
 };
 
 /// Operand Type - Operands are tagged with one of the values of this enum.
 enum MCOI_OperandType {
-       MCOI_OPERAND_UNKNOWN,
-       MCOI_OPERAND_IMMEDIATE,
-       MCOI_OPERAND_REGISTER,
-       MCOI_OPERAND_MEMORY,
-       MCOI_OPERAND_PCREL
+    MCOI_OPERAND_UNKNOWN,
+    MCOI_OPERAND_IMMEDIATE,
+    MCOI_OPERAND_REGISTER,
+    MCOI_OPERAND_MEMORY,
+    MCOI_OPERAND_PCREL
 };
 
 
@@ -53,22 +53,22 @@ enum MCOI_OperandType {
 /// instruction, indicating the register class for register operands, etc.
 ///
 typedef struct MCOperandInfo {
-       /// RegClass - This specifies the register class enumeration of the operand
-       /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
-       /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
-       /// get a dynamic register class.
-       int16_t RegClass;
-
-       /// Flags - These are flags from the MCOI::OperandFlags enum.
-       uint8_t Flags;
-
-       /// OperandType - Information about the type of the operand.
-       uint8_t OperandType;
-
-       /// Lower 16 bits are used to specify which constraints are set. The higher 16
-       /// bits are used to specify the value of constraints (4 bits each).
-       uint32_t Constraints;
-       /// Currently no other information.
+    /// RegClass - This specifies the register class enumeration of the operand
+    /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+    /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+    /// get a dynamic register class.
+    int16_t RegClass;
+
+    /// Flags - These are flags from the MCOI::OperandFlags enum.
+    uint8_t Flags;
+
+    /// OperandType - Information about the type of the operand.
+    uint8_t OperandType;
+
+    /// Lower 16 bits are used to specify which constraints are set. The higher 16
+    /// bits are used to specify the value of constraints (4 bits each).
+    uint32_t Constraints;
+    /// Currently no other information.
 } MCOperandInfo;
 
 
@@ -81,37 +81,37 @@ typedef struct MCOperandInfo {
 /// methods on MCInstrDesc, not use these directly.  These all correspond to
 /// bitfields in the MCInstrDesc::Flags field.
 enum {
-       MCID_Variadic = 0,
-       MCID_HasOptionalDef,
-       MCID_Pseudo,
-       MCID_Return,
-       MCID_Call,
-       MCID_Barrier,
-       MCID_Terminator,
-       MCID_Branch,
-       MCID_IndirectBranch,
-       MCID_Compare,
-       MCID_MoveImm,
-       MCID_Bitcast,
-       MCID_Select,
-       MCID_DelaySlot,
-       MCID_FoldableAsLoad,
-       MCID_MayLoad,
-       MCID_MayStore,
-       MCID_Predicable,
-       MCID_NotDuplicable,
-       MCID_UnmodeledSideEffects,
-       MCID_Commutable,
-       MCID_ConvertibleTo3Addr,
-       MCID_UsesCustomInserter,
-       MCID_HasPostISelHook,
-       MCID_Rematerializable,
-       MCID_CheapAsAMove,
-       MCID_ExtraSrcRegAllocReq,
-       MCID_ExtraDefRegAllocReq,
-       MCID_RegSequence,
-       MCID_ExtractSubreg,
-       MCID_InsertSubreg
+    MCID_Variadic = 0,
+    MCID_HasOptionalDef,
+    MCID_Pseudo,
+    MCID_Return,
+    MCID_Call,
+    MCID_Barrier,
+    MCID_Terminator,
+    MCID_Branch,
+    MCID_IndirectBranch,
+    MCID_Compare,
+    MCID_MoveImm,
+    MCID_Bitcast,
+    MCID_Select,
+    MCID_DelaySlot,
+    MCID_FoldableAsLoad,
+    MCID_MayLoad,
+    MCID_MayStore,
+    MCID_Predicable,
+    MCID_NotDuplicable,
+    MCID_UnmodeledSideEffects,
+    MCID_Commutable,
+    MCID_ConvertibleTo3Addr,
+    MCID_UsesCustomInserter,
+    MCID_HasPostISelHook,
+    MCID_Rematerializable,
+    MCID_CheapAsAMove,
+    MCID_ExtraSrcRegAllocReq,
+    MCID_ExtraDefRegAllocReq,
+    MCID_RegSequence,
+    MCID_ExtractSubreg,
+    MCID_InsertSubreg
 };
 
 /// MCInstrDesc - Describe properties that are true of each instruction in the
@@ -120,25 +120,25 @@ enum {
 /// for each target instruction class, and the MachineInstr class points to
 /// this struct directly to describe itself.
 typedef struct MCInstrDesc {
-       unsigned short  Opcode;        // The opcode number
-       unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
-       unsigned short  NumDefs;       // Num of args that are definitions
-       unsigned short  SchedClass;    // enum identifying instr sched class
-       unsigned short  Size;          // Number of bytes in encoding.
-       unsigned        Flags;         // Flags identifying machine instr class
-       uint64_t        TSFlags;       // Target Specific Flag values
-       uint16_t *ImplicitUses;  // Registers implicitly read by this instr
-       uint16_t *ImplicitDefs;  // Registers implicitly defined by this instr
-       MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
-       uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
-       // A complex method to determine is a certain is deprecated or not, and return        
-       // the reason for deprecation.
-       //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
-       unsigned ComplexDeprecationInfo;        // dummy field, just to satisfy initializer
+    unsigned short  Opcode;        // The opcode number
+    unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
+    unsigned char  NumDefs;       // Num of args that are definitions
+    unsigned short  SchedClass;    // enum identifying instr sched class
+    unsigned char  Size;          // Number of bytes in encoding.
+    unsigned        Flags;         // Flags identifying machine instr class
+    uint64_t        TSFlags;       // Target Specific Flag values
+    char ImplicitUses;  // Registers implicitly read by this instr
+    char ImplicitDefs;  // Registers implicitly defined by this instr
+    const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+    uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
+    // A complex method to determine is a certain is deprecated or not, and return        
+    // the reason for deprecation.
+    //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
+    unsigned char ComplexDeprecationInfo;    // dummy field, just to satisfy initializer
 } MCInstrDesc;
 
-bool MCOperandInfo_isPredicate(MCOperandInfo *m);
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
 
-bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
 
 #endif
index 026272b9bcd4a998b1dfd1f63ebfde7f7ecd0f83..091ed2829249894d9f92b3ea3b439ecfd5909297 100644 (file)
 /// Don't use this class directly, use one of the specialized sub-classes
 /// defined below.
 typedef struct DiffListIterator {
-       uint16_t Val;
-       MCPhysReg *List;
+    uint16_t Val;
+    const MCPhysReg *List;
 } DiffListIterator;
 
 void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
-               MCRegisterDesc *D, unsigned NR,
-               unsigned RA, unsigned PC,
-               MCRegisterClass *C, unsigned NC,
-               uint16_t (*RURoots)[2], unsigned NRU,
-               MCPhysReg *DL,
-               char *Strings,
-               uint16_t *SubIndices, unsigned NumIndices,
-               uint16_t *RET)
+        const MCRegisterDesc *D, unsigned NR,
+        unsigned RA, unsigned PC,
+        const MCRegisterClass *C, unsigned NC,
+        uint16_t (*RURoots)[2], unsigned NRU,
+        const MCPhysReg *DL,
+        const char *Strings,
+        const uint16_t *SubIndices, unsigned NumIndices,
+        const uint16_t *RET)
 {
-       RI->Desc = D;
-       RI->NumRegs = NR;
-       RI->RAReg = RA;
-       RI->PCReg = PC;
-       RI->Classes = C;
-       RI->DiffLists = DL;
-       RI->RegStrings = Strings;
-       RI->NumClasses = NC;
-       RI->RegUnitRoots = RURoots;
-       RI->NumRegUnits = NRU;
-       RI->SubRegIndices = SubIndices;
-       RI->NumSubRegIndices = NumIndices;
-       RI->RegEncodingTable = RET;
+    RI->Desc = D;
+    RI->NumRegs = NR;
+    RI->RAReg = RA;
+    RI->PCReg = PC;
+    RI->Classes = C;
+    RI->DiffLists = DL;
+    RI->RegStrings = Strings;
+    RI->NumClasses = NC;
+    RI->RegUnitRoots = RURoots;
+    RI->NumRegUnits = NRU;
+    RI->SubRegIndices = SubIndices;
+    RI->NumSubRegIndices = NumIndices;
+    RI->RegEncodingTable = RET;
 }
 
-static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
 {
-       d->Val = InitVal;
-       d->List = DiffList;
+    d->Val = InitVal;
+    d->List = DiffList;
 }
 
 static uint16_t DiffListIterator_getVal(DiffListIterator *d)
 {
-       return d->Val;
+    return d->Val;
 }
 
 static bool DiffListIterator_next(DiffListIterator *d)
 {
-       MCPhysReg D;
+    MCPhysReg D;
 
-       if (d->List == 0)
-               return false;
+    if (d->List == 0)
+        return false;
 
-       D = *d->List;
-       d->List++;
-       d->Val += D;
+    D = *d->List;
+    d->List++;
+    d->Val += D;
 
-       if (!D)
-               d->List = 0;
+    if (!D)
+        d->List = 0;
 
-       return (D != 0);
+    return (D != 0);
 }
 
 static bool DiffListIterator_isValid(DiffListIterator *d)
 {
-       return (d->List != 0);
+    return (d->List != 0);
 }
 
-unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
 {
-       DiffListIterator iter;
+    DiffListIterator iter;
 
-       if (Reg >= RI->NumRegs) {
-               return 0;
-       }
+    if (Reg >= RI->NumRegs) {
+        return 0;
+    }
 
-       DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
-       DiffListIterator_next(&iter);
+    DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+    DiffListIterator_next(&iter);
 
-       while(DiffListIterator_isValid(&iter)) {
-               uint16_t val = DiffListIterator_getVal(&iter);
-               if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
-                       return val;
+    while(DiffListIterator_isValid(&iter)) {
+        uint16_t val = DiffListIterator_getVal(&iter);
+        if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+            return val;
 
-               DiffListIterator_next(&iter);
-       }
+        DiffListIterator_next(&iter);
+    }
 
-       return 0;
+    return 0;
 }
 
-unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
 {
-       DiffListIterator iter;
-       uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+    DiffListIterator iter;
+    const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
 
-       DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
-       DiffListIterator_next(&iter);
+    DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+    DiffListIterator_next(&iter);
 
-       while(DiffListIterator_isValid(&iter)) {
-               if (*SRI == Idx)
-                       return DiffListIterator_getVal(&iter);
-               DiffListIterator_next(&iter);
-               ++SRI;
-       }
+    while(DiffListIterator_isValid(&iter)) {
+        if (*SRI == Idx)
+            return DiffListIterator_getVal(&iter);
+        DiffListIterator_next(&iter);
+        ++SRI;
+    }
 
-       return 0;
+    return 0;
 }
 
-MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
 {
-       //assert(i < getNumRegClasses() && "Register Class ID out of range");
-       if (i >= RI->NumClasses)
-               return 0;
-       return &(RI->Classes[i]);
+    //assert(i < getNumRegClasses() && "Register Class ID out of range");
+    if (i >= RI->NumClasses)
+        return 0;
+    return &(RI->Classes[i]);
 }
 
-bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
 {
-       unsigned InByte = Reg % 8;
-       unsigned Byte = Reg / 8;
+    unsigned InByte = Reg % 8;
+    unsigned Byte = Reg / 8;
 
-       if (Byte >= c->RegSetSize)
-               return false;
+    if (Byte >= c->RegSetSize)
+        return false;
 
-       return (c->RegSet[Byte] & (1 << InByte)) != 0;
+    return (c->RegSet[Byte] & (1 << InByte)) != 0;
 }
index 6d51e19195a204be151c7d7abbedfca2048d9082..4e3d9359d37415917fff5d8a1abab6d64926bcc2 100644 (file)
 /// An unsigned integer type large enough to represent all physical registers,
 /// but not necessarily virtual registers.
 typedef uint16_t MCPhysReg;
-typedef MCPhysReg* iterator;
+typedef const MCPhysReg* iterator;
 
 typedef struct MCRegisterClass {
-       iterator RegsBegin;
-       uint8_t *RegSet;
-       uint32_t NameIdx;
-       uint16_t RegsSize;
-       uint16_t RegSetSize;
-       uint16_t ID;
-       uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
-       int8_t CopyCost;
-       bool Allocatable;
+    iterator RegsBegin;
+    const uint8_t *RegSet;
+    uint32_t NameIdx;
+    uint16_t RegsSize;
+    uint16_t RegSetSize;
+    uint16_t ID;
+    uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+    int8_t CopyCost;
+    bool Allocatable;
 } MCRegisterClass;
 
 /// MCRegisterDesc - This record contains information about a particular
@@ -46,21 +46,21 @@ typedef struct MCRegisterClass {
 /// super-registers of AX.
 ///
 typedef struct MCRegisterDesc {
-       uint32_t Name;      // Printable name for the reg (for debugging)
-       uint32_t SubRegs;   // Sub-register set, described above
-       uint32_t SuperRegs; // Super-register set, described above
+    uint32_t Name;      // Printable name for the reg (for debugging)
+    uint32_t SubRegs;   // Sub-register set, described above
+    uint32_t SuperRegs; // Super-register set, described above
 
-       // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
-       // sub-register in SubRegs.
-       uint32_t SubRegIndices;
+    // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+    // sub-register in SubRegs.
+    uint32_t SubRegIndices;
 
-       // RegUnits - Points to the list of register units. The low 4 bits holds the
-       // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
-       uint32_t RegUnits;
+    // RegUnits - Points to the list of register units. The low 4 bits holds the
+    // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+    uint32_t RegUnits;
 
-       /// Index into list with lane mask sequences. The sequence contains a lanemask
-       /// for every register unit.
-       uint16_t RegUnitLaneMasks;
+    /// Index into list with lane mask sequences. The sequence contains a lanemask
+    /// for every register unit.
+    uint16_t RegUnitLaneMasks;
 } MCRegisterDesc;
 
 /// MCRegisterInfo base class - We assume that the target defines a static
@@ -76,41 +76,41 @@ typedef struct MCRegisterDesc {
 /// virtual methods.
 ///
 typedef struct MCRegisterInfo {
-       MCRegisterDesc *Desc;                 // Pointer to the descriptor array
-       unsigned NumRegs;                           // Number of entries in the array
-       unsigned RAReg;                             // Return address register
-       unsigned PCReg;                             // Program counter register
-       MCRegisterClass *Classes;             // Pointer to the regclass array
-       unsigned NumClasses;                        // Number of entries in the array
-       unsigned NumRegUnits;                       // Number of regunits.
-       uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
-       MCPhysReg *DiffLists;                 // Pointer to the difflists array
-       char *RegStrings;                     // Pointer to the string table.
-       uint16_t *SubRegIndices;              // Pointer to the subreg lookup
-       // array.
-       unsigned NumSubRegIndices;                  // Number of subreg indices.
-       uint16_t *RegEncodingTable;           // Pointer to array of register
-       // encodings.
+    const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+    unsigned NumRegs;                           // Number of entries in the array
+    unsigned RAReg;                             // Return address register
+    unsigned PCReg;                             // Program counter register
+    const MCRegisterClass *Classes;             // Pointer to the regclass array
+    unsigned NumClasses;                        // Number of entries in the array
+    unsigned NumRegUnits;                       // Number of regunits.
+    uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+    const MCPhysReg *DiffLists;                 // Pointer to the difflists array
+    const char *RegStrings;                     // Pointer to the string table.
+    const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+    // array.
+    unsigned NumSubRegIndices;                  // Number of subreg indices.
+    const uint16_t *RegEncodingTable;           // Pointer to array of register
+    // encodings.
 } MCRegisterInfo;
 
 void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
-               MCRegisterDesc *D, unsigned NR, unsigned RA,
-               unsigned PC,
-               MCRegisterClass *C, unsigned NC,
-               uint16_t (*RURoots)[2],
-               unsigned NRU,
-               MCPhysReg *DL,
-               char *Strings,
-               uint16_t *SubIndices,
-               unsigned NumIndices,
-               uint16_t *RET);
+        const MCRegisterDesc *D, unsigned NR, unsigned RA,
+        unsigned PC,
+        const MCRegisterClass *C, unsigned NC,
+        uint16_t (*RURoots)[2],
+        unsigned NRU,
+        const MCPhysReg *DL,
+        const char *Strings,
+        const uint16_t *SubIndices,
+        unsigned NumIndices,
+        const uint16_t *RET);
 
-unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
 
-unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
 
-MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
 
-bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
 
 #endif
index e9838e27ecd72261c1cd1951e4b6ebe5fecf7353..f841d556a0390f1cbeddcfb573a9fbff302f7a73 100644 (file)
@@ -2,12 +2,18 @@
 # By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
 
 include config.mk
-include pkgconfig.mk   # package version
+include pkgconfig.mk    # package version
 include functions.mk
 
 # Verbose output?
 V ?= 0
 
+OS := $(shell uname)
+ifeq ($(OS),Darwin)
+LIBARCHS ?= x86_64
+PREFIX ?= /usr/local
+endif
+
 ifeq ($(PKG_EXTRA),)
 PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
 else
@@ -15,10 +21,12 @@ PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
 endif
 
 ifeq ($(CROSS),)
-CC ?= cc
-AR ?= ar
 RANLIB ?= ranlib
-STRIP ?= strip
+else ifeq ($(ANDROID), 1)
+CC = $(CROSS)/../../bin/clang
+AR = $(CROSS)/ar
+RANLIB = $(CROSS)/ranlib
+STRIP = $(CROSS)/strip
 else
 CC = $(CROSS)gcc
 AR = $(CROSS)ar
@@ -37,7 +45,7 @@ ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
 CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
 endif
 
-CFLAGS += -fPIC -Wall -Iinclude
+CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude
 
 ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
 CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
@@ -47,10 +55,10 @@ ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
 CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
 SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
 CFLAGS += -mmacosx-version-min=10.5 \
-                 -isysroot$(SDKROOT) \
-                 -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
-                 -mkernel \
-                 -fno-builtin
+          -isysroot$(SDKROOT) \
+          -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
+          -mkernel \
+          -fno-builtin
 endif
 
 PREFIX ?= /usr
@@ -70,20 +78,20 @@ LIBDIRARCH ?= lib
 # Uncomment the below line to installs x86_64 libs to lib64/ directory.
 # Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
 #LIBDIRARCH ?= lib64
-LIBDIR ?= $(PREFIX)/$(LIBDIRARCH)
-BINDIR = $(PREFIX)/bin
+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
+BINDIR = $(DESTDIR)$(PREFIX)/bin
 
-LIBDATADIR ?= $(LIBDIR)
+LIBDATADIR = $(LIBDIR)
 
 # Don't redefine $LIBDATADIR when global environment variable
 # USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
 
 ifndef USE_GENERIC_LIBDATADIR
 ifeq ($(UNAME_S), FreeBSD)
-LIBDATADIR = $(PREFIX)/libdata
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
 endif
 ifeq ($(UNAME_S), DragonFly)
-LIBDATADIR = $(PREFIX)/libdata
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
 endif
 endif
 
@@ -99,9 +107,9 @@ DEP_ARM += $(wildcard arch/ARM/ARM*.inc)
 
 LIBOBJ_ARM =
 ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_ARM
-       LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
-       LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_ARM
+    LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
+    LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
 endif
 
 DEP_ARM64 =
@@ -109,9 +117,9 @@ DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
 
 LIBOBJ_ARM64 =
 ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_ARM64
-       LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
-       LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_ARM64
+    LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
+    LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -120,9 +128,9 @@ DEP_M68K += $(wildcard arch/M68K/M68K*.h)
 
 LIBOBJ_M68K =
 ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_M68K
-       LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
-       LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_M68K
+    LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
+    LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
 endif
 
 DEP_MIPS =
@@ -130,9 +138,9 @@ DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)
 
 LIBOBJ_MIPS =
 ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_MIPS
-       LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
-       LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_MIPS
+    LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
+    LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -141,9 +149,9 @@ DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)
 
 LIBOBJ_PPC =
 ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_POWERPC
-       LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
-       LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_POWERPC
+    LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
+    LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -152,9 +160,9 @@ DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)
 
 LIBOBJ_SPARC =
 ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_SPARC
-       LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
-       LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_SPARC
+    LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
+    LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -163,9 +171,9 @@ DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
 
 LIBOBJ_SYSZ =
 ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_SYSZ
-       LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
-       LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_SYSZ
+    LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
+    LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -188,18 +196,18 @@ DEP_X86 += arch/X86/X86ImmSize.inc
 
 LIBOBJ_X86 =
 ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_X86
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
+    CFLAGS += -DCAPSTONE_HAS_X86
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
 # assembly syntax is irrelevant in Diet mode, when this info is suppressed
 ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
 ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
 endif
 endif
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
-       LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
+    LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
 endif
 
 
@@ -208,9 +216,9 @@ DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)
 
 LIBOBJ_XCORE =
 ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_XCORE
-       LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
-       LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_XCORE
+    LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
+    LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -219,9 +227,9 @@ DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
 
 LIBOBJ_TMS320C64X =
 ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_TMS320C64X
-       LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
-       LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_TMS320C64X
+    LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
+    LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
 endif
 
 DEP_M680X =
@@ -230,9 +238,9 @@ DEP_M680X += $(wildcard arch/M680X/M680X*.h)
 
 LIBOBJ_M680X =
 ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_M680X
-       LIBSRC_M680X += $(wildcard arch/M680X/*.c)
-       LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_M680X
+    LIBSRC_M680X += $(wildcard arch/M680X/*.c)
+    LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -241,15 +249,27 @@ DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
 
 LIBOBJ_EVM =
 ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
-       CFLAGS += -DCAPSTONE_HAS_EVM
-       LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
-       LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
+    CFLAGS += -DCAPSTONE_HAS_EVM
+    LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
+    LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_MOS65XX =
+DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc)
+
+LIBOBJ_MOS65XX =
+ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS)))
+    CFLAGS += -DCAPSTONE_HAS_MOS65XX
+    LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c)
+    LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o)
 endif
 
 
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
-LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM)
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ)
+LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX)
 LIBOBJ += $(OBJDIR)/MCInst.o
 
 
@@ -267,8 +287,8 @@ VERSION_EXT =
 
 IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
 ifeq ($(IS_APPLE),1)
-# on MacOS, compile in Universal format by default
-MACOS_UNIVERSAL ?= yes
+# on MacOS, do not build in Universal format by default
+MACOS_UNIVERSAL ?= no
 ifeq ($(MACOS_UNIVERSAL),yes)
 CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
 LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
@@ -299,7 +319,7 @@ CFLAGS := $(CFLAGS:-fPIC=)
 # On Windows we need the shared library to be executable
 else
 # mingw?
-IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i mingw | wc -l)
+IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
 ifeq ($(IS_MINGW),1)
 EXT = dll
 AR_EXT = lib
@@ -321,7 +341,7 @@ ifeq ($(IS_MINGW),1)
 LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
 else ifeq ($(IS_CYGWIN),1)
 LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
-else   # *nix
+else    # *nix
 LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
 CFLAGS += -fvisibility=hidden
 endif
@@ -343,22 +363,24 @@ PKGCFGF = $(BLDIR)/$(LIBNAME).pc
 
 all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
 ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-       @V=$(V) CC=$(CC) $(MAKE) -C cstool
+    @V=$(V) CC=$(CC) $(MAKE) -C cstool
 ifndef BUILDDIR
-       cd tests && $(MAKE)
+    $(MAKE) -C tests
+    $(MAKE) -C suite/fuzz
 else
-       cd tests && $(MAKE) BUILDDIR=$(BLDIR)
+    $(MAKE) -C tests BUILDDIR=$(BLDIR)
+    $(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR)
 endif
-       $(call install-library,$(BLDIR)/tests/)
+    $(call install-library,$(BLDIR)/tests/)
 endif
 
 ifeq ($(CAPSTONE_SHARED),yes)
 $(LIBRARY): $(LIBOBJ)
 ifeq ($(V),0)
-       $(call log,LINK,$(@:$(BLDIR)/%=%))
-       @$(create-library)
+    $(call log,LINK,$(@:$(BLDIR)/%=%))
+    @$(create-library)
 else
-       $(create-library)
+    $(create-library)
 endif
 endif
 
@@ -376,64 +398,71 @@ $(LIBOBJ_XCORE): $(DEP_XCORE)
 $(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
 $(LIBOBJ_M680X): $(DEP_M680X)
 $(LIBOBJ_EVM): $(DEP_EVM)
+$(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
 
 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
-       @rm -f $(ARCHIVE)
+    @rm -f $(ARCHIVE)
 ifeq ($(V),0)
-       $(call log,AR,$(@:$(BLDIR)/%=%))
-       @$(create-archive)
+    $(call log,AR,$(@:$(BLDIR)/%=%))
+    @$(create-archive)
 else
-       $(create-archive)
+    $(create-archive)
 endif
 endif
 
 $(PKGCFGF):
 ifeq ($(V),0)
-       $(call log,GEN,$(@:$(BLDIR)/%=%))
-       @$(generate-pkgcfg)
+    $(call log,GEN,$(@:$(BLDIR)/%=%))
+    @$(generate-pkgcfg)
 else
-       $(generate-pkgcfg)
+    $(generate-pkgcfg)
 endif
 
 install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
-       mkdir -p $(DESTDIR)$(LIBDIR)
-       $(call install-library,$(DESTDIR)$(LIBDIR))
+    mkdir -p $(LIBDIR)
+    $(call install-library,$(LIBDIR))
 ifeq ($(CAPSTONE_STATIC),yes)
-       $(INSTALL_DATA) $(ARCHIVE) $(DESTDIR)$(LIBDIR)
+    $(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
+endif
+    mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
+    $(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
+    mkdir -p $(PKGCFGDIR)
+    $(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+    mkdir -p $(BINDIR)
+    $(INSTALL_LIB) cstool/cstool $(BINDIR)
 endif
-       mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
-       $(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
-       mkdir -p $(DESTDIR)$(PKGCFGDIR)
-       $(INSTALL_DATA) $(PKGCFGF) $(DESTDIR)$(PKGCFGDIR)
-       mkdir -p $(DESTDIR)$(BINDIR)
-       $(INSTALL_LIB) cstool/cstool $(DESTDIR)$(BINDIR)
 
 uninstall:
-       rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
-       rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).*
-       rm -f $(DESTDIR)$(PKGCFGDIR)/$(LIBNAME).pc
-       rm -f $(DESTDIR)$(BINDIR)/cstool
+    rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
+    rm -f $(LIBDIR)/lib$(LIBNAME).*
+    rm -f $(PKGCFGDIR)/$(LIBNAME).pc
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+    rm -f $(BINDIR)/cstool
+endif
 
 clean:
-       rm -f $(LIBOBJ)
-       rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
-       rm -f $(PKGCFGF)
-       $(MAKE) -C cstool clean
+    rm -f $(LIBOBJ)
+    rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
+    rm -f $(PKGCFGF)
+    [ "${ANDROID}" = "1" ] && rm -rf android-ndk-* || true
 
 ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-       cd tests && $(MAKE) clean
-       rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
+    $(MAKE) -C cstool clean
+    $(MAKE) -C tests clean
+    $(MAKE) -C suite/fuzz clean
+    rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
 endif
 
 ifdef BUILDDIR
-       rm -rf $(BUILDDIR)
+    rm -rf $(BUILDDIR)
 endif
 
 ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
-       cd bindings/python && $(MAKE) clean
-       cd bindings/java && $(MAKE) clean
-       cd bindings/ocaml && $(MAKE) clean
+    $(MAKE) -C bindings/python clean
+    $(MAKE) -C bindings/java clean
+    $(MAKE) -C bindings/ocaml clean
 endif
 
 
@@ -445,39 +474,50 @@ DIST_VERSION = $(TAG)
 endif
 
 dist:
-       git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
-       git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
+    git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
+    git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
 
 TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
-TESTS += test_systemz test_x86 test_xcore test_iter
+TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_mos65xx
 TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
 TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
-TESTS += test_skipdata test_skipdata.static test_iter.static
-check:
-       @for t in $(TESTS); do \
-               echo Check $$t ... ; \
-               LD_LIBRARY_PATH=./tests ./tests/$$t > /dev/null && echo OK || echo FAILED; \
-       done
+TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static
+TESTS += test_mos65xx.static
+check: $(TESTS) fuzztest fuzzallcorp
+test_%:
+    ./tests/$@ > /dev/null && echo OK || echo FAILED
+
+FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
+
+fuzztest:
+    ./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS)
+
+fuzzallcorp:
+ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),)
+    ./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/
+else
+    @echo "Skipping tests on whole corpus"
+endif
 
 $(OBJDIR)/%.o: %.c
-       @mkdir -p $(@D)
+    @mkdir -p $(@D)
 ifeq ($(V),0)
-       $(call log,CC,$(@:$(OBJDIR)/%=%))
-       @$(compile)
+    $(call log,CC,$(@:$(OBJDIR)/%=%))
+    @$(compile)
 else
-       $(compile)
+    $(compile)
 endif
 
 
 ifeq ($(CAPSTONE_SHARED),yes)
 define install-library
-       $(INSTALL_LIB) $(LIBRARY) $1
-       $(if $(VERSION_EXT),
-               cd $1 && \
-               rm -f lib$(LIBNAME).$(EXT) && \
-               ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
+    $(INSTALL_LIB) $(LIBRARY) $1
+    $(if $(VERSION_EXT),
+        cd $1 && \
+        rm -f lib$(LIBNAME).$(EXT) && \
+        ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
 endef
 else
 define install-library
@@ -486,24 +526,24 @@ endif
 
 
 define create-archive
-       $(AR) q $(ARCHIVE) $(LIBOBJ)
-       $(RANLIB) $(ARCHIVE)
+    $(AR) q $(ARCHIVE) $(LIBOBJ)
+    $(RANLIB) $(ARCHIVE)
 endef
 
 
 define create-library
-       $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+    $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
 endef
 
 
 define generate-pkgcfg
-       mkdir -p $(BLDIR)
-       echo 'Name: capstone' > $(PKGCFGF)
-       echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
-       echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
-       echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
-       echo 'includedir=$(INCDIR)' >> $(PKGCFGF)
-       echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
-       echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
-       echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
+    mkdir -p $(BLDIR)
+    echo 'Name: capstone' > $(PKGCFGF)
+    echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
+    echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
+    echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
+    echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
+    echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
+    echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
+    echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
 endef
index 3292f73f7ca10124f8113b017a59030aecc0b1ff..441e70b7f97e930c802c9e18d7ccb80c88ed6e4e 100644 (file)
 
 /// Hi_32 - This function returns the high 32 bits of a 64 bit value.
 static inline uint32_t Hi_32(uint64_t Value) {
-       return (uint32_t)(Value >> 32);
+    return (uint32_t)(Value >> 32);
 }
 
 /// Lo_32 - This function returns the low 32 bits of a 64 bit value.
 static inline uint32_t Lo_32(uint64_t Value) {
-       return (uint32_t)(Value);
+    return (uint32_t)(Value);
 }
 
 /// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
 /// bit width.
 static inline bool isUIntN(unsigned N, uint64_t x) {
-       return x == (x & (~0ULL >> (64 - N)));
+    return x == (x & (~0ULL >> (64 - N)));
 }
 
 /// isIntN - Checks if an signed integer fits into the given (dynamic)
@@ -59,33 +59,33 @@ static inline bool isUIntN(unsigned N, uint64_t x) {
 /// starting at the least significant bit with the remainder zero (32 bit
 /// version).   Ex. isMask_32(0x0000FFFFU) == true.
 static inline bool isMask_32(uint32_t Value) {
-       return Value && ((Value + 1) & Value) == 0;
+    return Value && ((Value + 1) & Value) == 0;
 }
 
 /// isMask_64 - This function returns true if the argument is a sequence of ones
 /// starting at the least significant bit with the remainder zero (64 bit
 /// version).
 static inline bool isMask_64(uint64_t Value) {
-       return Value && ((Value + 1) & Value) == 0;
+    return Value && ((Value + 1) & Value) == 0;
 }
 
 /// isShiftedMask_32 - This function returns true if the argument contains a
 /// sequence of ones with the remainder zero (32 bit version.)
 /// Ex. isShiftedMask_32(0x0000FF00U) == true.
 static inline bool isShiftedMask_32(uint32_t Value) {
-       return isMask_32((Value - 1) | Value);
+    return isMask_32((Value - 1) | Value);
 }
 
 /// isShiftedMask_64 - This function returns true if the argument contains a
 /// sequence of ones with the remainder zero (64 bit version.)
 static inline bool isShiftedMask_64(uint64_t Value) {
-       return isMask_64((Value - 1) | Value);
+    return isMask_64((Value - 1) | Value);
 }
 
 /// isPowerOf2_32 - This function returns true if the argument is a power of
 /// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
 static inline bool isPowerOf2_32(uint32_t Value) {
-       return Value && !(Value & (Value - 1));
+    return Value && !(Value & (Value - 1));
 }
 
 /// CountLeadingZeros_32 - this function performs the platform optimal form of
@@ -93,28 +93,28 @@ static inline bool isPowerOf2_32(uint32_t Value) {
 /// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
 /// Returns 32 if the word is zero.
 static inline unsigned CountLeadingZeros_32(uint32_t Value) {
-       unsigned Count; // result
+    unsigned Count; // result
 #if __GNUC__ >= 4
-       // PowerPC is defined for __builtin_clz(0)
+    // PowerPC is defined for __builtin_clz(0)
 #if !defined(__ppc__) && !defined(__ppc64__)
-       if (!Value) return 32;
+    if (!Value) return 32;
 #endif
-       Count = __builtin_clz(Value);
+    Count = __builtin_clz(Value);
 #else
-       unsigned Shift;
-       if (!Value) return 32;
-       Count = 0;
-       // bisection method for count leading zeros
-       for (Shift = 32 >> 1; Shift; Shift >>= 1) {
-               uint32_t Tmp = Value >> Shift;
-               if (Tmp) {
-                       Value = Tmp;
-               } else {
-                       Count |= Shift;
-               }
-       }
+    unsigned Shift;
+    if (!Value) return 32;
+    Count = 0;
+    // bisection method for count leading zeros
+    for (Shift = 32 >> 1; Shift; Shift >>= 1) {
+        uint32_t Tmp = Value >> Shift;
+        if (Tmp) {
+            Value = Tmp;
+        } else {
+            Count |= Shift;
+        }
+    }
 #endif
-       return Count;
+    return Count;
 }
 
 /// CountLeadingOnes_32 - this function performs the operation of
@@ -122,7 +122,7 @@ static inline unsigned CountLeadingZeros_32(uint32_t Value) {
 /// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
 /// Returns 32 if the word is all ones.
 static inline unsigned CountLeadingOnes_32(uint32_t Value) {
-       return CountLeadingZeros_32(~Value);
+    return CountLeadingZeros_32(~Value);
 }
 
 /// CountLeadingZeros_64 - This function performs the platform optimal form
@@ -130,49 +130,49 @@ static inline unsigned CountLeadingOnes_32(uint32_t Value) {
 /// one bit (64 bit edition.)
 /// Returns 64 if the word is zero.
 static inline unsigned CountLeadingZeros_64(uint64_t Value) {
-       unsigned Count; // result
+    unsigned Count; // result
 #if __GNUC__ >= 4
-       // PowerPC is defined for __builtin_clzll(0)
+    // PowerPC is defined for __builtin_clzll(0)
 #if !defined(__ppc__) && !defined(__ppc64__)
-       if (!Value) return 64;
+    if (!Value) return 64;
 #endif
-       Count = __builtin_clzll(Value);
+    Count = __builtin_clzll(Value);
 #else
 #ifndef _MSC_VER
-       unsigned Shift;
-       if (sizeof(long) == sizeof(int64_t))
-       {
-               if (!Value) return 64;
-               Count = 0;
-               // bisection method for count leading zeros
-               for (Shift = 64 >> 1; Shift; Shift >>= 1) {
-                       uint64_t Tmp = Value >> Shift;
-                       if (Tmp) {
-                               Value = Tmp;
-                       } else {
-                               Count |= Shift;
-                       }
-               }
-       }
-       else
+    unsigned Shift;
+    if (sizeof(long) == sizeof(int64_t))
+    {
+        if (!Value) return 64;
+        Count = 0;
+        // bisection method for count leading zeros
+        for (Shift = 64 >> 1; Shift; Shift >>= 1) {
+            uint64_t Tmp = Value >> Shift;
+            if (Tmp) {
+                Value = Tmp;
+            } else {
+                Count |= Shift;
+            }
+        }
+    }
+    else
 #endif
-       {
-               // get hi portion
-               uint32_t Hi = Hi_32(Value);
-
-               // if some bits in hi portion
-               if (Hi) {
-                       // leading zeros in hi portion plus all bits in lo portion
-                       Count = CountLeadingZeros_32(Hi);
-               } else {
-                       // get lo portion
-                       uint32_t Lo = Lo_32(Value);
-                       // same as 32 bit value
-                       Count = CountLeadingZeros_32(Lo)+32;
-               }
-       }
+    {
+        // get hi portion
+        uint32_t Hi = Hi_32(Value);
+
+        // if some bits in hi portion
+        if (Hi) {
+            // leading zeros in hi portion plus all bits in lo portion
+            Count = CountLeadingZeros_32(Hi);
+        } else {
+            // get lo portion
+            uint32_t Lo = Lo_32(Value);
+            // same as 32 bit value
+            Count = CountLeadingZeros_32(Lo)+32;
+        }
+    }
 #endif
-       return Count;
+    return Count;
 }
 
 /// CountLeadingOnes_64 - This function performs the operation
@@ -180,7 +180,7 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) {
 /// zero bit (64 bit edition.)
 /// Returns 64 if the word is all ones.
 static inline unsigned CountLeadingOnes_64(uint64_t Value) {
-       return CountLeadingZeros_64(~Value);
+    return CountLeadingZeros_64(~Value);
 }
 
 /// CountTrailingZeros_32 - this function performs the platform optimal form of
@@ -189,17 +189,17 @@ static inline unsigned CountLeadingOnes_64(uint64_t Value) {
 /// Returns 32 if the word is zero.
 static inline unsigned CountTrailingZeros_32(uint32_t Value) {
 #if __GNUC__ >= 4
-       return Value ? __builtin_ctz(Value) : 32;
+    return Value ? __builtin_ctz(Value) : 32;
 #else
-       static const unsigned Mod37BitPosition[] = {
-               32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
-               4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
-               5, 20, 8, 19, 18
-       };
-       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
-       // MSVC warning C4146
-       //    return Mod37BitPosition[(-Value & Value) % 37];
-       return Mod37BitPosition[((1 + ~Value) & Value) % 37];
+    static const unsigned Mod37BitPosition[] = {
+        32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
+        4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
+        5, 20, 8, 19, 18
+    };
+    // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+    // MSVC warning C4146
+    //    return Mod37BitPosition[(-Value & Value) % 37];
+    return Mod37BitPosition[((1 + ~Value) & Value) % 37];
 #endif
 }
 
@@ -208,7 +208,7 @@ static inline unsigned CountTrailingZeros_32(uint32_t Value) {
 /// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
 /// Returns 32 if the word is all ones.
 static inline unsigned CountTrailingOnes_32(uint32_t Value) {
-       return CountTrailingZeros_32(~Value);
+    return CountTrailingZeros_32(~Value);
 }
 
 /// CountTrailingZeros_64 - This function performs the platform optimal form
@@ -217,19 +217,19 @@ static inline unsigned CountTrailingOnes_32(uint32_t Value) {
 /// Returns 64 if the word is zero.
 static inline unsigned CountTrailingZeros_64(uint64_t Value) {
 #if __GNUC__ >= 4
-       return Value ? __builtin_ctzll(Value) : 64;
+    return Value ? __builtin_ctzll(Value) : 64;
 #else
-       static const unsigned Mod67Position[] = {
-               64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
-               4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
-               47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
-               29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
-               7, 48, 35, 6, 34, 33, 0
-       };
-       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
-       // MSVC warning C4146
-       //    return Mod67Position[(-Value & Value) % 67];
-       return Mod67Position[((1 + ~Value) & Value) % 67];
+    static const unsigned Mod67Position[] = {
+        64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
+        4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
+        47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
+        29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
+        7, 48, 35, 6, 34, 33, 0
+    };
+    // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+    // MSVC warning C4146
+    //    return Mod67Position[(-Value & Value) % 67];
+    return Mod67Position[((1 + ~Value) & Value) % 67];
 #endif
 }
 
@@ -238,7 +238,7 @@ static inline unsigned CountTrailingZeros_64(uint64_t Value) {
 /// zero bit (64 bit edition.)
 /// Returns 64 if the word is all ones.
 static inline unsigned CountTrailingOnes_64(uint64_t Value) {
-       return CountTrailingZeros_64(~Value);
+    return CountTrailingZeros_64(~Value);
 }
 
 /// CountPopulation_32 - this function counts the number of set bits in a value.
@@ -246,11 +246,11 @@ static inline unsigned CountTrailingOnes_64(uint64_t Value) {
 /// Returns 0 if the word is zero.
 static inline unsigned CountPopulation_32(uint32_t Value) {
 #if __GNUC__ >= 4
-       return __builtin_popcount(Value);
+    return __builtin_popcount(Value);
 #else
-       uint32_t v = Value - ((Value >> 1) & 0x55555555);
-       v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
-       return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
+    uint32_t v = Value - ((Value >> 1) & 0x55555555);
+    v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+    return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
 #endif
 }
 
@@ -258,12 +258,12 @@ static inline unsigned CountPopulation_32(uint32_t Value) {
 /// (64 bit edition.)
 static inline unsigned CountPopulation_64(uint64_t Value) {
 #if __GNUC__ >= 4
-       return __builtin_popcountll(Value);
+    return __builtin_popcountll(Value);
 #else
-       uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
-       v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
-       v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
-       return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
+    uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
+    v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
+    v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+    return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
 #endif
 }
 
@@ -271,59 +271,59 @@ static inline unsigned CountPopulation_64(uint64_t Value) {
 /// -1 if the value is zero. (32 bit edition.)
 /// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
 static inline unsigned Log2_32(uint32_t Value) {
-       return 31 - CountLeadingZeros_32(Value);
+    return 31 - CountLeadingZeros_32(Value);
 }
 
 /// Log2_64 - This function returns the floor log base 2 of the specified value,
 /// -1 if the value is zero. (64 bit edition.)
 static inline unsigned Log2_64(uint64_t Value) {
-       return 63 - CountLeadingZeros_64(Value);
+    return 63 - CountLeadingZeros_64(Value);
 }
 
 /// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
 /// value, 32 if the value is zero. (32 bit edition).
 /// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
 static inline unsigned Log2_32_Ceil(uint32_t Value) {
-       return 32-CountLeadingZeros_32(Value-1);
+    return 32-CountLeadingZeros_32(Value-1);
 }
 
 /// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
 /// value, 64 if the value is zero. (64 bit edition.)
 static inline unsigned Log2_64_Ceil(uint64_t Value) {
-       return 64-CountLeadingZeros_64(Value-1);
+    return 64-CountLeadingZeros_64(Value-1);
 }
 
 /// GreatestCommonDivisor64 - Return the greatest common divisor of the two
 /// values using Euclid's algorithm.
 static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
-       while (B) {
-               uint64_t T = B;
-               B = A % B;
-               A = T;
-       }
-       return A;
+    while (B) {
+        uint64_t T = B;
+        B = A % B;
+        A = T;
+    }
+    return A;
 }
 
 /// BitsToDouble - This function takes a 64-bit integer and returns the bit
 /// equivalent double.
 static inline double BitsToDouble(uint64_t Bits) {
-       union {
-               uint64_t L;
-               double D;
-       } T;
-       T.L = Bits;
-       return T.D;
+    union {
+        uint64_t L;
+        double D;
+    } T;
+    T.L = Bits;
+    return T.D;
 }
 
 /// BitsToFloat - This function takes a 32-bit integer and returns the bit
 /// equivalent float.
 static inline float BitsToFloat(uint32_t Bits) {
-       union {
-               uint32_t I;
-               float F;
-       } T;
-       T.I = Bits;
-       return T.F;
+    union {
+        uint32_t I;
+        float F;
+    } T;
+    T.I = Bits;
+    return T.F;
 }
 
 /// DoubleToBits - This function takes a double and returns the bit
@@ -331,12 +331,12 @@ static inline float BitsToFloat(uint32_t Bits) {
 /// changes the bits of NaNs on some hosts, notably x86, so this
 /// routine cannot be used if these bits are needed.
 static inline uint64_t DoubleToBits(double Double) {
-       union {
-               uint64_t L;
-               double D;
-       } T;
-       T.D = Double;
-       return T.L;
+    union {
+        uint64_t L;
+        double D;
+    } T;
+    T.D = Double;
+    return T.L;
 }
 
 /// FloatToBits - This function takes a float and returns the bit
@@ -344,35 +344,35 @@ static inline uint64_t DoubleToBits(double Double) {
 /// changes the bits of NaNs on some hosts, notably x86, so this
 /// routine cannot be used if these bits are needed.
 static inline uint32_t FloatToBits(float Float) {
-       union {
-               uint32_t I;
-               float F;
-       } T;
-       T.F = Float;
-       return T.I;
+    union {
+        uint32_t I;
+        float F;
+    } T;
+    T.F = Float;
+    return T.I;
 }
 
 /// MinAlign - A and B are either alignments or offsets.  Return the minimum
 /// alignment that may be assumed after adding the two together.
 static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
-       // The largest power of 2 that divides both A and B.
-       //
-       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
-       // MSVC warning C4146
-       //    return (A | B) & -(A | B);
-       return (A | B) & (1 + ~(A | B));
+    // The largest power of 2 that divides both A and B.
+    //
+    // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+    // MSVC warning C4146
+    //    return (A | B) & -(A | B);
+    return (A | B) & (1 + ~(A | B));
 }
 
 /// NextPowerOf2 - Returns the next power of two (in 64-bits)
 /// that is strictly greater than A.  Returns zero on overflow.
 static inline uint64_t NextPowerOf2(uint64_t A) {
-       A |= (A >> 1);
-       A |= (A >> 2);
-       A |= (A >> 4);
-       A |= (A >> 8);
-       A |= (A >> 16);
-       A |= (A >> 32);
-       return A + 1;
+    A |= (A >> 1);
+    A |= (A >> 2);
+    A |= (A >> 4);
+    A |= (A >> 8);
+    A |= (A >> 16);
+    A |= (A >> 32);
+    return A + 1;
 }
 
 /// Returns the next integer (mod 2**64) that is greater than or equal to
@@ -385,33 +385,33 @@ static inline uint64_t NextPowerOf2(uint64_t A) {
 ///   RoundUpToAlignment(~0LL, 8) = 0
 /// \endcode
 static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
-       return ((Value + Align - 1) / Align) * Align;
+    return ((Value + Align - 1) / Align) * Align;
 }
 
 /// Returns the offset to the next integer (mod 2**64) that is greater than
 /// or equal to \p Value and is a multiple of \p Align. \p Align must be
 /// non-zero.
 static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
-       return RoundUpToAlignment(Value, Align) - Value;
+    return RoundUpToAlignment(Value, Align) - Value;
 }
 
 /// abs64 - absolute value of a 64-bit int.  Not all environments support
 /// "abs" on whatever their name for the 64-bit int type is.  The absolute
 /// value of the largest negative number is undefined, as with "abs".
 static inline int64_t abs64(int64_t x) {
-       return (x < 0) ? -x : x;
+    return (x < 0) ? -x : x;
 }
 
 /// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
 /// Requires 0 < B <= 32.
 static inline int32_t SignExtend32(uint32_t X, unsigned B) {
-       return (int32_t)(X << (32 - B)) >> (32 - B);
+    return (int32_t)(X << (32 - B)) >> (32 - B);
 }
 
 /// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
 /// Requires 0 < B <= 64.
 static inline int64_t SignExtend64(uint64_t X, unsigned B) {
-       return (int64_t)(X << (64 - B)) >> (64 - B);
+    return (int64_t)(X << (64 - B)) >> (64 - B);
 }
 
 /// \brief Count number of 0's from the most significant bit to the least
@@ -423,17 +423,20 @@ static inline int64_t SignExtend64(uint64_t X, unsigned B) {
 ///   valid arguments.
 static inline unsigned int countLeadingZeros(int x)
 {
-       unsigned count = 0;
-       int i;
-       const unsigned bits = sizeof(x) * 8;
-
-       for (i = bits; --i; ) {
-               if (x < 0) break;
-               count++;
-               x <<= 1;
-       }
-
-       return count;
+    int i;
+    const unsigned bits = sizeof(x) * 8;
+    unsigned count = bits;
+
+    if (x < 0) {
+        return 0;
+    }
+    for (i = bits; --i; ) {
+        if (x == 0) break;
+        count--;
+        x >>= 1;
+    }
+
+    return count;
 }
 
 #endif
index e25acef5ea6b66db09c366a01437177dfa80f9d9..1a61b9484a3d7624de0ef1b94cc705ad67712700 100644 (file)
@@ -1,8 +1,10 @@
 Capstone Engine
 ===============
 
-[![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=next)](https://travis-ci.org/aquynh/capstone)
-[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/next?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/next)
+[![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=master)](https://travis-ci.org/aquynh/capstone)
+[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/master?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/master)
+[![pypi package](https://badge.fury.io/py/capstone.svg)](https://pypi.python.org/pypi/capstone)
+[![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone)
 
 Capstone is a disassembly framework with the target of becoming the ultimate
 disasm engine for binary analysis and reversing in the security community.
@@ -11,7 +13,7 @@ Created by Nguyen Anh Quynh, then developed and maintained by a small community,
 Capstone offers some unparalleled features:
 
 - Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K,
-  Mips, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).
+  Mips, MOS65XX, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).
 
 - Having clean/simple/lightweight/intuitive architecture-neutral API.
 
@@ -20,13 +22,13 @@ Capstone offers some unparalleled features:
 - Provide semantics of the disassembled instruction, such as list of implicit
   registers read & written.
 
-- Implemented in pure C language, with lightweight bindings for PHP, PowerShell,
-  Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua,
-  Rust, Delphi, Free Pascal & Vala ready either in main code, or provided
-  externally by the community).
+- Implemented in pure C language, with lightweight bindings for D, Clojure, F#,
+  Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python,
+  Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala
+  (ready either in main code, or provided externally by the community).
 
 - Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
-  Linux, *BSD, Solaris, etc.
+  Linux, \*BSD, Solaris, etc.
 
 - Thread-safe by design.
 
diff --git a/Source/ThirdParty/capstone/Source/SPONSORS.TXT b/Source/ThirdParty/capstone/Source/SPONSORS.TXT
new file mode 100644 (file)
index 0000000..e737e2a
--- /dev/null
@@ -0,0 +1,20 @@
+* Version 4.0.1 - January 10th, 2019
+
+Release 4.0.1 was sponsored by the following companies (in no particular order).
+
+- NowSecure: https://www.nowsecure.com
+- Verichains: https://verichains.io
+- Vsec: https://vsec.com.vn
+
+-----------------------------------
+* Version 4.0 - December 18th, 2018
+
+Capstone 4.0 version marks 5 years of the project!
+This release was sponsored by the following companies (in no particular order).
+
+- Thinkst Canary: https://canary.tools
+- NowSecure: https://www.nowsecure.com
+- ECQ: https://e-cq.net
+- Senrio: https://senr.io
+- GracefulBits: https://gracefulbits.com
+- Catena Cyber: https://catenacyber.fr
index a332f89beb6237554781764557af9ad8c65118c8..9afeb58e06e208320018d6d25be17965c72a7d44 100644 (file)
@@ -3,9 +3,12 @@
 
 #include <stdarg.h>
 #if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
 #include <libkern/libkern.h>
+#include <i386/limits.h>
 #else
 #include <stdio.h>
+#include <limits.h>
 #endif
 #include <string.h>
 
 
 void SStream_Init(SStream *ss)
 {
-       ss->index = 0;
-       ss->buffer[0] = '\0';
+    ss->index = 0;
+    ss->buffer[0] = '\0';
 }
 
-void SStream_concat0(SStream *ss, char *s)
+void SStream_concat0(SStream *ss, const char *s)
 {
 #ifndef CAPSTONE_DIET
-       unsigned int len = (unsigned int) strlen(s);
+    unsigned int len = (unsigned int) strlen(s);
 
-       memcpy(ss->buffer + ss->index, s, len);
-       ss->index += len;
-       ss->buffer[ss->index] = '\0';
+    memcpy(ss->buffer + ss->index, s, len);
+    ss->index += len;
+    ss->buffer[ss->index] = '\0';
 #endif
 }
 
 void SStream_concat(SStream *ss, const char *fmt, ...)
 {
 #ifndef CAPSTONE_DIET
-       va_list ap;
-       int ret;
+    va_list ap;
+    int ret;
 
-       va_start(ap, fmt);
-       ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
-       va_end(ap);
-       ss->index += ret;
+    va_start(ap, fmt);
+    ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+    va_end(ap);
+    ss->index += ret;
 #endif
 }
 
 // print number with prefix #
 void printInt64Bang(SStream *O, int64_t val)
 {
-       if (val >= 0) {
-               if (val > HEX_THRESHOLD)
-                       SStream_concat(O, "#0x%"PRIx64, val);
-               else
-                       SStream_concat(O, "#%"PRIu64, val);
-       } else {
-               if (val <- HEX_THRESHOLD)
-                       SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val);
-               else
-                       SStream_concat(O, "#-%"PRIu64, -val);
-       }
+    if (val >= 0) {
+        if (val > HEX_THRESHOLD)
+            SStream_concat(O, "#0x%"PRIx64, val);
+        else
+            SStream_concat(O, "#%"PRIu64, val);
+    } else {
+        if (val <- HEX_THRESHOLD) {
+            if (val == LONG_MIN)
+                SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val);
+            else
+                SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val);
+        }
+        else
+            SStream_concat(O, "#-%"PRIu64, -val);
+    }
 }
 
 void printUInt64Bang(SStream *O, uint64_t val)
 {
-       if (val > HEX_THRESHOLD)
-               SStream_concat(O, "#0x%"PRIx64, val);
-       else
-               SStream_concat(O, "#%"PRIu64, val);
+    if (val > HEX_THRESHOLD)
+        SStream_concat(O, "#0x%"PRIx64, val);
+    else
+        SStream_concat(O, "#%"PRIu64, val);
 }
 
 // print number
 void printInt64(SStream *O, int64_t val)
 {
-       if (val >= 0) {
-               if (val > HEX_THRESHOLD)
-                       SStream_concat(O, "0x%"PRIx64, val);
-               else
-                       SStream_concat(O, "%"PRIu64, val);
-       } else {
-               if (val <- HEX_THRESHOLD)
-                       SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val);
-               else
-                       SStream_concat(O, "-%"PRIu64, -val);
-       }
+    if (val >= 0) {
+        if (val > HEX_THRESHOLD)
+            SStream_concat(O, "0x%"PRIx64, val);
+        else
+            SStream_concat(O, "%"PRIu64, val);
+    } else {
+        if (val <- HEX_THRESHOLD) {
+            if (val == LONG_MIN)
+                SStream_concat(O, "-0x%"PRIx64, (uint64_t)val);
+            else
+                SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val);
+        }
+        else
+            SStream_concat(O, "-%"PRIu64, -val);
+    }
 }
 
 // print number in decimal mode
 void printInt32BangDec(SStream *O, int32_t val)
 {
-       if (val >= 0)
-               SStream_concat(O, "#%u", val);
-       else
-               SStream_concat(O, "#-%u", (uint32_t)-val);
+    if (val >= 0)
+        SStream_concat(O, "#%u", val);
+    else
+        if (val == INT_MIN)
+            SStream_concat(O, "#-%u", val);
+        else
+            SStream_concat(O, "#-%u", (uint32_t)-val);
 }
 
 void printInt32Bang(SStream *O, int32_t val)
 {
-       if (val >= 0) {
-               if (val > HEX_THRESHOLD)
-                       SStream_concat(O, "#0x%x", val);
-               else
-                       SStream_concat(O, "#%u", val);
-       } else {
-               if (val <- HEX_THRESHOLD)
-                       SStream_concat(O, "#-0x%x", (uint32_t)-val);
-               else
-                       SStream_concat(O, "#-%u", -val);
-       }
+    if (val >= 0) {
+        if (val > HEX_THRESHOLD)
+            SStream_concat(O, "#0x%x", val);
+        else
+            SStream_concat(O, "#%u", val);
+    } else {
+        if (val <- HEX_THRESHOLD) {
+            if (val == INT_MIN)
+                SStream_concat(O, "#-0x%x", (uint32_t)val);
+            else
+                SStream_concat(O, "#-0x%x", (uint32_t)-val);
+        }
+        else
+            SStream_concat(O, "#-%u", -val);
+    }
 }
 
 void printInt32(SStream *O, int32_t val)
 {
-       if (val >= 0) {
-               if (val > HEX_THRESHOLD)
-                       SStream_concat(O, "0x%x", val);
-               else
-                       SStream_concat(O, "%u", val);
-       } else {
-               if (val <- HEX_THRESHOLD)
-                       SStream_concat(O, "-0x%x", (uint32_t)-val);
-               else
-                       SStream_concat(O, "-%u", -val);
-       }
+    if (val >= 0) {
+        if (val > HEX_THRESHOLD)
+            SStream_concat(O, "0x%x", val);
+        else
+            SStream_concat(O, "%u", val);
+    } else {
+        if (val <- HEX_THRESHOLD) {
+            if (val == INT_MIN)
+                SStream_concat(O, "-0x%x", (uint32_t)val);
+            else
+                SStream_concat(O, "-0x%x", (uint32_t)-val);
+            }
+        else
+            SStream_concat(O, "-%u", -val);
+    }
 }
 
 void printUInt32Bang(SStream *O, uint32_t val)
 {
-       if (val > HEX_THRESHOLD)
-               SStream_concat(O, "#0x%x", val);
-       else
-               SStream_concat(O, "#%u", val);
+    if (val > HEX_THRESHOLD)
+        SStream_concat(O, "#0x%x", val);
+    else
+        SStream_concat(O, "#%u", val);
 }
 
 void printUInt32(SStream *O, uint32_t val)
 {
-       if (val > HEX_THRESHOLD)
-               SStream_concat(O, "0x%x", val);
-       else
-               SStream_concat(O, "%u", val);
+    if (val > HEX_THRESHOLD)
+        SStream_concat(O, "0x%x", val);
+    else
+        SStream_concat(O, "%u", val);
 }
 
 /*
index 9ccd35109c5eba55fc7aed1be7ecfc5597bb9d6b..1579a70c64e6139d00764a1ef12d142213a3f712 100644 (file)
@@ -7,15 +7,15 @@
 #include "include/capstone/platform.h"
 
 typedef struct SStream {
-       char buffer[512];
-       int index;
+    char buffer[512];
+    int index;
 } SStream;
 
 void SStream_Init(SStream *ss);
 
 void SStream_concat(SStream *ss, const char *fmt, ...);
 
-void SStream_concat0(SStream *ss, char *s);
+void SStream_concat0(SStream *ss, const char *s);
 
 void printInt64Bang(SStream *O, int64_t val);
 
index d4540bb0617f0ee77528947d4d2d21ec9d16cd20..848c6ceca67baea61b14cc37234b99e15a2eaa57 100644 (file)
 
 /// ARM_AM - ARM Addressing Mode Stuff
 typedef enum ARM_AM_ShiftOpc {
-       ARM_AM_no_shift = 0,
-       ARM_AM_asr,
-       ARM_AM_lsl,
-       ARM_AM_lsr,
-       ARM_AM_ror,
-       ARM_AM_rrx
+    ARM_AM_no_shift = 0,
+    ARM_AM_asr,
+    ARM_AM_lsl,
+    ARM_AM_lsr,
+    ARM_AM_ror,
+    ARM_AM_rrx
 } ARM_AM_ShiftOpc;
 
 typedef enum ARM_AM_AddrOpc {
-       ARM_AM_sub = 0,
-       ARM_AM_add
+    ARM_AM_sub = 0,
+    ARM_AM_add
 } ARM_AM_AddrOpc;
 
-static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
+static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
 {
-       return Op == ARM_AM_sub ? "-" : "";
+    return Op == ARM_AM_sub ? "-" : "";
 }
 
-static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
+static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
 {
-       switch (Op) {
-               default: return "";     //llvm_unreachable("Unknown shift opc!");
-               case ARM_AM_asr: return "asr";
-               case ARM_AM_lsl: return "lsl";
-               case ARM_AM_lsr: return "lsr";
-               case ARM_AM_ror: return "ror";
-               case ARM_AM_rrx: return "rrx";
-       }
+    switch (Op) {
+        default: return "";    //llvm_unreachable("Unknown shift opc!");
+        case ARM_AM_asr: return "asr";
+        case ARM_AM_lsl: return "lsl";
+        case ARM_AM_lsr: return "lsr";
+        case ARM_AM_ror: return "ror";
+        case ARM_AM_rrx: return "rrx";
+    }
 }
 
 static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
 {
-       switch (Op) {
-               default: return (unsigned int)-1;       //llvm_unreachable("Unknown shift opc!");
-               case ARM_AM_asr: return 2;
-               case ARM_AM_lsl: return 0;
-               case ARM_AM_lsr: return 1;
-               case ARM_AM_ror: return 3;
-       }
+    switch (Op) {
+        default: return (unsigned int)-1;    //llvm_unreachable("Unknown shift opc!");
+        case ARM_AM_asr: return 2;
+        case ARM_AM_lsl: return 0;
+        case ARM_AM_lsr: return 1;
+        case ARM_AM_ror: return 3;
+    }
 }
 
 typedef enum ARM_AM_AMSubMode {
-       ARM_AM_bad_am_submode = 0,
-       ARM_AM_ia,
-       ARM_AM_ib,
-       ARM_AM_da,
-       ARM_AM_db
+    ARM_AM_bad_am_submode = 0,
+    ARM_AM_ia,
+    ARM_AM_ib,
+    ARM_AM_da,
+    ARM_AM_db
 } ARM_AM_AMSubMode;
 
 static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
 {
-       switch (Mode) {
-               default: return "";
-               case ARM_AM_ia: return "ia";
-               case ARM_AM_ib: return "ib";
-               case ARM_AM_da: return "da";
-               case ARM_AM_db: return "db";
-       }
+    switch (Mode) {
+        default: return "";
+        case ARM_AM_ia: return "ia";
+        case ARM_AM_ib: return "ib";
+        case ARM_AM_da: return "da";
+        case ARM_AM_db: return "db";
+    }
 }
 
 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
 ///
 static inline unsigned rotr32(unsigned Val, unsigned Amt)
 {
-       //assert(Amt < 32 && "Invalid rotate amount");
-       return (Val >> Amt) | (Val << ((32-Amt)&31));
+    //assert(Amt < 32 && "Invalid rotate amount");
+    return (Val >> Amt) | (Val << ((32-Amt)&31));
 }
 
 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
 ///
 static inline unsigned rotl32(unsigned Val, unsigned Amt)
 {
-       //assert(Amt < 32 && "Invalid rotate amount");
-       return (Val << Amt) | (Val >> ((32-Amt)&31));
+    //assert(Amt < 32 && "Invalid rotate amount");
+    return (Val << Amt) | (Val >> ((32-Amt)&31));
 }
 
 //===--------------------------------------------------------------------===//
@@ -114,31 +114,31 @@ static inline unsigned rotl32(unsigned Val, unsigned Amt)
 //
 static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
 {
-       return ShOp | (Imm << 3);
+    return ShOp | (Imm << 3);
 }
 
 static inline unsigned getSORegOffset(unsigned Op)
 {
-       return Op >> 3;
+    return Op >> 3;
 }
 
 static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 {
-       return (ARM_AM_ShiftOpc)(Op & 7);
+    return (ARM_AM_ShiftOpc)(Op & 7);
 }
 
 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
 /// the 8-bit imm value.
 static inline unsigned getSOImmValImm(unsigned Imm)
 {
-       return Imm & 0xFF;
+    return Imm & 0xFF;
 }
 
 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
 /// the rotate amount.
 static inline unsigned getSOImmValRot(unsigned Imm)
 {
-       return (Imm >> 8) * 2;
+    return (Imm >> 8) * 2;
 }
 
 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
@@ -147,35 +147,35 @@ static inline unsigned getSOImmValRot(unsigned Imm)
 /// take a maximal chunk of bits out of the immediate.
 static inline unsigned getSOImmValRotate(unsigned Imm)
 {
-       unsigned TZ, RotAmt;
-       // 8-bit (or less) immediates are trivially shifter_operands with a rotate
-       // of zero.
-       if ((Imm & ~255U) == 0) return 0;
+    unsigned TZ, RotAmt;
+    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
+    // of zero.
+    if ((Imm & ~255U) == 0) return 0;
 
-       // Use CTZ to compute the rotate amount.
-       TZ = CountTrailingZeros_32(Imm);
+    // Use CTZ to compute the rotate amount.
+    TZ = CountTrailingZeros_32(Imm);
 
-       // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
-       // not 9.
-       RotAmt = TZ & ~1;
+    // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
+    // not 9.
+    RotAmt = TZ & ~1;
 
-       // If we can handle this spread, return it.
-       if ((rotr32(Imm, RotAmt) & ~255U) == 0)
-               return (32-RotAmt)&31;  // HW rotates right, not left.
+    // If we can handle this spread, return it.
+    if ((rotr32(Imm, RotAmt) & ~255U) == 0)
+        return (32-RotAmt)&31;  // HW rotates right, not left.
 
-       // For values like 0xF000000F, we should ignore the low 6 bits, then
-       // retry the hunt.
-       if (Imm & 63U) {
-               unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
-               unsigned RotAmt2 = TZ2 & ~1;
-               if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
-                       return (32-RotAmt2)&31;  // HW rotates right, not left.
-       }
+    // For values like 0xF000000F, we should ignore the low 6 bits, then
+    // retry the hunt.
+    if (Imm & 63U) {
+        unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
+        unsigned RotAmt2 = TZ2 & ~1;
+        if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
+            return (32-RotAmt2)&31;  // HW rotates right, not left.
+    }
 
-       // Otherwise, we have no way to cover this span of bits with a single
-       // shifter_op immediate.  Return a chunk of bits that will be useful to
-       // handle.
-       return (32-RotAmt)&31;  // HW rotates right, not left.
+    // Otherwise, we have no way to cover this span of bits with a single
+    // shifter_op immediate.  Return a chunk of bits that will be useful to
+    // handle.
+    return (32-RotAmt)&31;  // HW rotates right, not left.
 }
 
 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
@@ -183,101 +183,101 @@ static inline unsigned getSOImmValRotate(unsigned Imm)
 /// it.  If not, return -1.
 static inline int getSOImmVal(unsigned Arg)
 {
-       unsigned RotAmt;
-       // 8-bit (or less) immediates are trivially shifter_operands with a rotate
-       // of zero.
-       if ((Arg & ~255U) == 0) return Arg;
+    unsigned RotAmt;
+    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
+    // of zero.
+    if ((Arg & ~255U) == 0) return Arg;
 
-       RotAmt = getSOImmValRotate(Arg);
+    RotAmt = getSOImmValRotate(Arg);
 
-       // If this cannot be handled with a single shifter_op, bail out.
-       if (rotr32(~255U, RotAmt) & Arg)
-               return -1;
+    // If this cannot be handled with a single shifter_op, bail out.
+    if (rotr32(~255U, RotAmt) & Arg)
+        return -1;
 
-       // Encode this correctly.
-       return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+    // Encode this correctly.
+    return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
 }
 
 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
 /// or'ing together two SOImmVal's.
 static inline bool isSOImmTwoPartVal(unsigned V)
 {
-       // If this can be handled with a single shifter_op, bail out.
-       V = rotr32(~255U, getSOImmValRotate(V)) & V;
-       if (V == 0)
-               return false;
+    // If this can be handled with a single shifter_op, bail out.
+    V = rotr32(~255U, getSOImmValRotate(V)) & V;
+    if (V == 0)
+        return false;
 
-       // If this can be handled with two shifter_op's, accept.
-       V = rotr32(~255U, getSOImmValRotate(V)) & V;
-       return V == 0;
+    // If this can be handled with two shifter_op's, accept.
+    V = rotr32(~255U, getSOImmValRotate(V)) & V;
+    return V == 0;
 }
 
 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the first chunk of it.
 static inline unsigned getSOImmTwoPartFirst(unsigned V)
 {
-       return rotr32(255U, getSOImmValRotate(V)) & V;
+    return rotr32(255U, getSOImmValRotate(V)) & V;
 }
 
 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the second chunk of it.
 static inline unsigned getSOImmTwoPartSecond(unsigned V)
 {
-       // Mask out the first hunk.
-       V = rotr32(~255U, getSOImmValRotate(V)) & V;
+    // Mask out the first hunk.
+    V = rotr32(~255U, getSOImmValRotate(V)) & V;
 
-       // Take what's left.
-       //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
-       return V;
+    // Take what's left.
+    //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+    return V;
 }
 
 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
 static inline unsigned getThumbImmValShift(unsigned Imm)
 {
-       // 8-bit (or less) immediates are trivially immediate operand with a shift
-       // of zero.
-       if ((Imm & ~255U) == 0) return 0;
+    // 8-bit (or less) immediates are trivially immediate operand with a shift
+    // of zero.
+    if ((Imm & ~255U) == 0) return 0;
 
-       // Use CTZ to compute the shift amount.
-       return CountTrailingZeros_32(Imm);
+    // Use CTZ to compute the shift amount.
+    return CountTrailingZeros_32(Imm);
 }
 
 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
 /// by left shifting a 8-bit immediate.
 static inline bool isThumbImmShiftedVal(unsigned V)
 {
-       // If this can be handled with
-       V = (~255U << getThumbImmValShift(V)) & V;
-       return V == 0;
+    // If this can be handled with
+    V = (~255U << getThumbImmValShift(V)) & V;
+    return V == 0;
 }
 
 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
 static inline unsigned getThumbImm16ValShift(unsigned Imm)
 {
-       // 16-bit (or less) immediates are trivially immediate operand with a shift
-       // of zero.
-       if ((Imm & ~65535U) == 0) return 0;
+    // 16-bit (or less) immediates are trivially immediate operand with a shift
+    // of zero.
+    if ((Imm & ~65535U) == 0) return 0;
 
-       // Use CTZ to compute the shift amount.
-       return CountTrailingZeros_32(Imm);
+    // Use CTZ to compute the shift amount.
+    return CountTrailingZeros_32(Imm);
 }
 
 /// isThumbImm16ShiftedVal - Return true if the specified value can be
 /// obtained by left shifting a 16-bit immediate.
 static inline bool isThumbImm16ShiftedVal(unsigned V)
 {
-       // If this can be handled with
-       V = (~65535U << getThumbImm16ValShift(V)) & V;
-       return V == 0;
+    // If this can be handled with
+    V = (~65535U << getThumbImm16ValShift(V)) & V;
+    return V == 0;
 }
 
 /// getThumbImmNonShiftedVal - If V is a value that satisfies
 /// isThumbImmShiftedVal, return the non-shiftd value.
 static inline unsigned getThumbImmNonShiftedVal(unsigned V)
 {
-       return V >> getThumbImmValShift(V);
+    return V >> getThumbImmValShift(V);
 }
 
 
@@ -292,27 +292,27 @@ static inline unsigned getThumbImmNonShiftedVal(unsigned V)
 /// See ARM Reference Manual A6.3.2.
 static inline int getT2SOImmValSplatVal(unsigned V)
 {
-       unsigned u, Vs, Imm;
-       // control = 0
-       if ((V & 0xffffff00) == 0)
-               return V;
+    unsigned u, Vs, Imm;
+    // control = 0
+    if ((V & 0xffffff00) == 0)
+        return V;
 
-       // If the value is zeroes in the first byte, just shift those off
-       Vs = ((V & 0xff) == 0) ? V >> 8 : V;
-       // Any passing value only has 8 bits of payload, splatted across the word
-       Imm = Vs & 0xff;
-       // Likewise, any passing values have the payload splatted into the 3rd byte
-       u = Imm | (Imm << 16);
+    // If the value is zeroes in the first byte, just shift those off
+    Vs = ((V & 0xff) == 0) ? V >> 8 : V;
+    // Any passing value only has 8 bits of payload, splatted across the word
+    Imm = Vs & 0xff;
+    // Likewise, any passing values have the payload splatted into the 3rd byte
+    u = Imm | (Imm << 16);
 
-       // control = 1 or 2
-       if (Vs == u)
-               return (((Vs == V) ? 1 : 2) << 8) | Imm;
+    // control = 1 or 2
+    if (Vs == u)
+        return (((Vs == V) ? 1 : 2) << 8) | Imm;
 
-       // control = 3
-       if (Vs == (u | (u << 8)))
-               return (3 << 8) | Imm;
+    // control = 3
+    if (Vs == (u | (u << 8)))
+        return (3 << 8) | Imm;
 
-       return -1;
+    return -1;
 }
 
 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
@@ -321,15 +321,15 @@ static inline int getT2SOImmValSplatVal(unsigned V)
 /// See ARM Reference Manual A6.3.2.
 static inline int getT2SOImmValRotateVal(unsigned V)
 {
-       unsigned RotAmt = CountLeadingZeros_32(V);
-       if (RotAmt >= 24)
-               return -1;
+    unsigned RotAmt = CountLeadingZeros_32(V);
+    if (RotAmt >= 24)
+        return -1;
 
-       // If 'Arg' can be handled with a single shifter_op return the value.
-       if ((rotr32(0xff000000U, RotAmt) & V) == V)
-               return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+    // If 'Arg' can be handled with a single shifter_op return the value.
+    if ((rotr32(0xff000000U, RotAmt) & V) == V)
+        return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
 
-       return -1;
+    return -1;
 }
 
 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
@@ -338,86 +338,86 @@ static inline int getT2SOImmValRotateVal(unsigned V)
 /// See ARM Reference Manual A6.3.2.
 static inline int getT2SOImmVal(unsigned Arg)
 {
-       int Rot;
-       // If 'Arg' is an 8-bit splat, then get the encoded value.
-       int Splat = getT2SOImmValSplatVal(Arg);
-       if (Splat != -1)
-               return Splat;
+    int Rot;
+    // If 'Arg' is an 8-bit splat, then get the encoded value.
+    int Splat = getT2SOImmValSplatVal(Arg);
+    if (Splat != -1)
+        return Splat;
 
-       // If 'Arg' can be handled with a single shifter_op return the value.
-       Rot = getT2SOImmValRotateVal(Arg);
-       if (Rot != -1)
-               return Rot;
+    // If 'Arg' can be handled with a single shifter_op return the value.
+    Rot = getT2SOImmValRotateVal(Arg);
+    if (Rot != -1)
+        return Rot;
 
-       return -1;
+    return -1;
 }
 
 static inline unsigned getT2SOImmValRotate(unsigned V)
 {
-       unsigned RotAmt;
+    unsigned RotAmt;
 
-       if ((V & ~255U) == 0)
-               return 0;
+    if ((V & ~255U) == 0)
+        return 0;
 
-       // Use CTZ to compute the rotate amount.
-       RotAmt = CountTrailingZeros_32(V);
-       return (32 - RotAmt) & 31;
+    // Use CTZ to compute the rotate amount.
+    RotAmt = CountTrailingZeros_32(V);
+    return (32 - RotAmt) & 31;
 }
 
 static inline bool isT2SOImmTwoPartVal (unsigned Imm)
 {
-       unsigned V = Imm;
-       // Passing values can be any combination of splat values and shifter
-       // values. If this can be handled with a single shifter or splat, bail
-       // out. Those should be handled directly, not with a two-part val.
-       if (getT2SOImmValSplatVal(V) != -1)
-               return false;
-       V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
-       if (V == 0)
-               return false;
+    unsigned V = Imm;
+    // Passing values can be any combination of splat values and shifter
+    // values. If this can be handled with a single shifter or splat, bail
+    // out. Those should be handled directly, not with a two-part val.
+    if (getT2SOImmValSplatVal(V) != -1)
+        return false;
+    V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+    if (V == 0)
+        return false;
 
-       // If this can be handled as an immediate, accept.
-       if (getT2SOImmVal(V) != -1) return true;
+    // If this can be handled as an immediate, accept.
+    if (getT2SOImmVal(V) != -1) return true;
 
-       // Likewise, try masking out a splat value first.
-       V = Imm;
-       if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
-               V &= ~0xff00ff00U;
-       else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
-               V &= ~0x00ff00ffU;
-       // If what's left can be handled as an immediate, accept.
-       if (getT2SOImmVal(V) != -1) return true;
+    // Likewise, try masking out a splat value first.
+    V = Imm;
+    if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+        V &= ~0xff00ff00U;
+    else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+        V &= ~0x00ff00ffU;
+    // If what's left can be handled as an immediate, accept.
+    if (getT2SOImmVal(V) != -1) return true;
 
-       // Otherwise, do not accept.
-       return false;
+    // Otherwise, do not accept.
+    return false;
 }
 
 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
 {
-       //assert (isT2SOImmTwoPartVal(Imm) &&
-       //        "Immedate cannot be encoded as two part immediate!");
-       // Try a shifter operand as one part
-       unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
-       // If the rest is encodable as an immediate, then return it.
-       if (getT2SOImmVal(V) != -1) return V;
+    //assert (isT2SOImmTwoPartVal(Imm) &&
+    //        "Immedate cannot be encoded as two part immediate!");
+    // Try a shifter operand as one part
+    unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
+    // If the rest is encodable as an immediate, then return it.
+    if (getT2SOImmVal(V) != -1) return V;
 
-       // Try masking out a splat value first.
-       if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
-               return Imm & 0xff00ff00U;
+    // Try masking out a splat value first.
+    if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+        return Imm & 0xff00ff00U;
 
-       // The other splat is all that's left as an option.
-       //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
-       return Imm & 0x00ff00ffU;
+    // The other splat is all that's left as an option.
+    //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+    return Imm & 0x00ff00ffU;
 }
 
 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
 {
-       // Mask out the first hunk
-       Imm ^= getT2SOImmTwoPartFirst(Imm);
-       // Return what's left
-       //assert (getT2SOImmVal(Imm) != -1 &&
-       //        "Unable to encode second part of T2 two part SO immediate");
-       return Imm;
+    // Mask out the first hunk
+    Imm ^= getT2SOImmTwoPartFirst(Imm);
+    // Return what's left
+    //assert (getT2SOImmVal(Imm) != -1 &&
+    //        "Unable to encode second part of T2 two part SO immediate");
+    return Imm;
 }
 
 
@@ -440,31 +440,31 @@ static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
 // with no shift amount for the frame offset.
 //
 static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
-               unsigned IdxMode)
+        unsigned IdxMode)
 {
-       //assert(Imm12 < (1 << 12) && "Imm too large!");
-       bool isSub = Opc == ARM_AM_sub;
-       return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
+    //assert(Imm12 < (1 << 12) && "Imm too large!");
+    bool isSub = Opc == ARM_AM_sub;
+    return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
 }
 
 static inline unsigned getAM2Offset(unsigned AM2Opc)
 {
-       return AM2Opc & ((1 << 12)-1);
+    return AM2Opc & ((1 << 12)-1);
 }
 
 static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
 {
-       return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
+    return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
 static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
 {
-       return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
+    return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
 }
 
 static inline unsigned getAM2IdxMode(unsigned AM2Opc)
 {
-       return (AM2Opc >> 16);
+    return (AM2Opc >> 16);
 }
 
 //===--------------------------------------------------------------------===//
@@ -483,25 +483,25 @@ static inline unsigned getAM2IdxMode(unsigned AM2Opc)
 
 /// getAM3Opc - This function encodes the addrmode3 opc field.
 static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
-               unsigned IdxMode)
+        unsigned IdxMode)
 {
-       bool isSub = Opc == ARM_AM_sub;
-       return ((int)isSub << 8) | Offset | (IdxMode << 9);
+    bool isSub = Opc == ARM_AM_sub;
+    return ((int)isSub << 8) | Offset | (IdxMode << 9);
 }
 
 static inline unsigned char getAM3Offset(unsigned AM3Opc)
 {
-       return AM3Opc & 0xFF;
+    return AM3Opc & 0xFF;
 }
 
 static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
 {
-       return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+    return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
 static inline unsigned getAM3IdxMode(unsigned AM3Opc)
 {
-       return (AM3Opc >> 9);
+    return (AM3Opc >> 9);
 }
 
 //===--------------------------------------------------------------------===//
@@ -521,12 +521,12 @@ static inline unsigned getAM3IdxMode(unsigned AM3Opc)
 
 static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
 {
-       return (ARM_AM_AMSubMode)(Mode & 0x7);
+    return (ARM_AM_AMSubMode)(Mode & 0x7);
 }
 
 static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
 {
-       return (int)SubMode;
+    return (int)SubMode;
 }
 
 //===--------------------------------------------------------------------===//
@@ -543,16 +543,16 @@ static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
 /// getAM5Opc - This function encodes the addrmode5 opc field.
 static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
 {
-       bool isSub = Opc == ARM_AM_sub;
-       return ((int)isSub << 8) | Offset;
+    bool isSub = Opc == ARM_AM_sub;
+    return ((int)isSub << 8) | Offset;
 }
 static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
 {
-       return AM5Opc & 0xFF;
+    return AM5Opc & 0xFF;
 }
 static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 {
-       return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+    return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
 //===--------------------------------------------------------------------===//
@@ -582,15 +582,15 @@ static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 
 static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
 {
-       return (OpCmode << 8) | Val;
+    return (OpCmode << 8) | Val;
 }
 static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
 {
-       return (ModImm >> 8) & 0x1f;
+    return (ModImm >> 8) & 0x1f;
 }
 static inline unsigned getNEONModImmVal(unsigned ModImm)
 {
-       return ModImm & 0xff;
+    return ModImm & 0xff;
 }
 
 /// decodeNEONModImm - Decode a NEON modified immediate value into the
@@ -598,41 +598,41 @@ static inline unsigned getNEONModImmVal(unsigned ModImm)
 /// smaller than the vector, it is splatted into all the elements.)
 static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
 {
-       unsigned OpCmode = getNEONModImmOpCmode(ModImm);
-       unsigned Imm8 = getNEONModImmVal(ModImm);
-       uint64_t Val = 0;
-       unsigned ByteNum;
-
-       if (OpCmode == 0xe) {
-               // 8-bit vector elements
-               Val = Imm8;
-               *EltBits = 8;
-       } else if ((OpCmode & 0xc) == 0x8) {
-               // 16-bit vector elements
-               ByteNum = (OpCmode & 0x6) >> 1;
-               Val = (uint64_t)Imm8 << (8 * ByteNum);
-               *EltBits = 16;
-       } else if ((OpCmode & 0x8) == 0) {
-               // 32-bit vector elements, zero with one byte set
-               ByteNum = (OpCmode & 0x6) >> 1;
-               Val = (uint64_t)Imm8 << (8 * ByteNum);
-               *EltBits = 32;
-       } else if ((OpCmode & 0xe) == 0xc) {
-               // 32-bit vector elements, one byte with low bits set
-               ByteNum = 1 + (OpCmode & 0x1);
-               Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
-               *EltBits = 32;
-       } else if (OpCmode == 0x1e) {
-               // 64-bit vector elements
-               for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
-                       if ((ModImm >> ByteNum) & 1)
-                               Val |= (uint64_t)0xff << (8 * ByteNum);
-               }
-               *EltBits = 64;
-       } else {
-               //llvm_unreachable("Unsupported NEON immediate");
-       }
-       return Val;
+    unsigned OpCmode = getNEONModImmOpCmode(ModImm);
+    unsigned Imm8 = getNEONModImmVal(ModImm);
+    uint64_t Val = 0;
+    unsigned ByteNum;
+
+    if (OpCmode == 0xe) {
+        // 8-bit vector elements
+        Val = Imm8;
+        *EltBits = 8;
+    } else if ((OpCmode & 0xc) == 0x8) {
+        // 16-bit vector elements
+        ByteNum = (OpCmode & 0x6) >> 1;
+        Val = (uint64_t)Imm8 << (8 * ByteNum);
+        *EltBits = 16;
+    } else if ((OpCmode & 0x8) == 0) {
+        // 32-bit vector elements, zero with one byte set
+        ByteNum = (OpCmode & 0x6) >> 1;
+        Val = (uint64_t)Imm8 << (8 * ByteNum);
+        *EltBits = 32;
+    } else if ((OpCmode & 0xe) == 0xc) {
+        // 32-bit vector elements, one byte with low bits set
+        ByteNum = 1 + (OpCmode & 0x1);
+        Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
+        *EltBits = 32;
+    } else if (OpCmode == 0x1e) {
+        // 64-bit vector elements
+        for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+            if ((ModImm >> ByteNum) & 1)
+                Val |= (uint64_t)0xff << (8 * ByteNum);
+        }
+        *EltBits = 64;
+    } else {
+        //llvm_unreachable("Unsupported NEON immediate");
+    }
+    return Val;
 }
 
 ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
@@ -642,28 +642,28 @@ ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
 //
 static inline float getFPImmFloat(unsigned Imm)
 {
-       // We expect an 8-bit binary encoding of a floating-point number here.
-       union {
-               uint32_t I;
-               float F;
-       } FPUnion;
-
-       uint8_t Sign = (Imm >> 7) & 0x1;
-       uint8_t Exp = (Imm >> 4) & 0x7;
-       uint8_t Mantissa = Imm & 0xf;
-
-       //   8-bit FP    iEEEE Float Encoding
-       //   abcd efgh   aBbbbbbc defgh000 00000000 00000000
-       //
-       // where B = NOT(b);
-
-       FPUnion.I = 0;
-       FPUnion.I |= Sign << 31;
-       FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
-       FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
-       FPUnion.I |= (Exp & 0x3) << 23;
-       FPUnion.I |= Mantissa << 19;
-       return FPUnion.F;
+    // We expect an 8-bit binary encoding of a floating-point number here.
+    union {
+        uint32_t I;
+        float F;
+    } FPUnion;
+
+    uint8_t Sign = (Imm >> 7) & 0x1;
+    uint8_t Exp = (Imm >> 4) & 0x7;
+    uint8_t Mantissa = Imm & 0xf;
+
+    //   8-bit FP    iEEEE Float Encoding
+    //   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+    //
+    // where B = NOT(b);
+
+    FPUnion.I = 0;
+    FPUnion.I |= ((uint32_t) Sign) << 31;
+    FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+    FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+    FPUnion.I |= (Exp & 0x3) << 23;
+    FPUnion.I |= Mantissa << 19;
+    return FPUnion.F;
 }
 
 #endif
index 9fc4979fcef78ef37e0355713fdc9e5a350f75b2..8a1979a82a769be5d2e63e4028723e33a8384ab8 100644 (file)
 // The CondCodes constants map directly to the 4-bit encoding of the
 // condition field for predicated instructions.
 typedef enum ARMCC_CondCodes { // Meaning (integer)          Meaning (floating-point)
-       ARMCC_EQ,            // Equal                      Equal
-       ARMCC_NE,            // Not equal                  Not equal, or unordered
-       ARMCC_HS,            // Carry set                  >, ==, or unordered
-       ARMCC_LO,            // Carry clear                Less than
-       ARMCC_MI,            // Minus, negative            Less than
-       ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
-       ARMCC_VS,            // Overflow                   Unordered
-       ARMCC_VC,            // No overflow                Not unordered
-       ARMCC_HI,            // Unsigned higher            Greater than, or unordered
-       ARMCC_LS,            // Unsigned lower or same     Less than or equal
-       ARMCC_GE,            // Greater than or equal      Greater than or equal
-       ARMCC_LT,            // Less than                  Less than, or unordered
-       ARMCC_GT,            // Greater than               Greater than
-       ARMCC_LE,            // Less than or equal         <, ==, or unordered
-       ARMCC_AL             // Always (unconditional)     Always (unconditional)
+    ARMCC_EQ,            // Equal                      Equal
+    ARMCC_NE,            // Not equal                  Not equal, or unordered
+    ARMCC_HS,            // Carry set                  >, ==, or unordered
+    ARMCC_LO,            // Carry clear                Less than
+    ARMCC_MI,            // Minus, negative            Less than
+    ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
+    ARMCC_VS,            // Overflow                   Unordered
+    ARMCC_VC,            // No overflow                Not unordered
+    ARMCC_HI,            // Unsigned higher            Greater than, or unordered
+    ARMCC_LS,            // Unsigned lower or same     Less than or equal
+    ARMCC_GE,            // Greater than or equal      Greater than or equal
+    ARMCC_LT,            // Less than                  Less than, or unordered
+    ARMCC_GT,            // Greater than               Greater than
+    ARMCC_LE,            // Less than or equal         <, ==, or unordered
+    ARMCC_AL             // Always (unconditional)     Always (unconditional)
 } ARMCC_CondCodes;
 
 inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
 {
-       switch (CC) {
-               case ARMCC_EQ: return ARMCC_NE;
-               case ARMCC_NE: return ARMCC_EQ;
-               case ARMCC_HS: return ARMCC_LO;
-               case ARMCC_LO: return ARMCC_HS;
-               case ARMCC_MI: return ARMCC_PL;
-               case ARMCC_PL: return ARMCC_MI;
-               case ARMCC_VS: return ARMCC_VC;
-               case ARMCC_VC: return ARMCC_VS;
-               case ARMCC_HI: return ARMCC_LS;
-               case ARMCC_LS: return ARMCC_HI;
-               case ARMCC_GE: return ARMCC_LT;
-               case ARMCC_LT: return ARMCC_GE;
-               case ARMCC_GT: return ARMCC_LE;
-               case ARMCC_LE: return ARMCC_GT;
-               default: return ARMCC_AL;
-       }
+    switch (CC) {
+        case ARMCC_EQ: return ARMCC_NE;
+        case ARMCC_NE: return ARMCC_EQ;
+        case ARMCC_HS: return ARMCC_LO;
+        case ARMCC_LO: return ARMCC_HS;
+        case ARMCC_MI: return ARMCC_PL;
+        case ARMCC_PL: return ARMCC_MI;
+        case ARMCC_VS: return ARMCC_VC;
+        case ARMCC_VC: return ARMCC_VS;
+        case ARMCC_HI: return ARMCC_LS;
+        case ARMCC_LS: return ARMCC_HI;
+        case ARMCC_GE: return ARMCC_LT;
+        case ARMCC_LT: return ARMCC_GE;
+        case ARMCC_GT: return ARMCC_LE;
+        case ARMCC_LE: return ARMCC_GT;
+        default: return ARMCC_AL;
+    }
 }
 
-inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
 {
-       switch (CC) {
-               case ARMCC_EQ:  return "eq";
-               case ARMCC_NE:  return "ne";
-               case ARMCC_HS:  return "hs";
-               case ARMCC_LO:  return "lo";
-               case ARMCC_MI:  return "mi";
-               case ARMCC_PL:  return "pl";
-               case ARMCC_VS:  return "vs";
-               case ARMCC_VC:  return "vc";
-               case ARMCC_HI:  return "hi";
-               case ARMCC_LS:  return "ls";
-               case ARMCC_GE:  return "ge";
-               case ARMCC_LT:  return "lt";
-               case ARMCC_GT:  return "gt";
-               case ARMCC_LE:  return "le";
-               case ARMCC_AL:  return "al";
-               default: return "";
-       }
+    switch (CC) {
+        case ARMCC_EQ:  return "eq";
+        case ARMCC_NE:  return "ne";
+        case ARMCC_HS:  return "hs";
+        case ARMCC_LO:  return "lo";
+        case ARMCC_MI:  return "mi";
+        case ARMCC_PL:  return "pl";
+        case ARMCC_VS:  return "vs";
+        case ARMCC_VC:  return "vc";
+        case ARMCC_HI:  return "hi";
+        case ARMCC_LS:  return "ls";
+        case ARMCC_GE:  return "ge";
+        case ARMCC_LT:  return "lt";
+        case ARMCC_GT:  return "gt";
+        case ARMCC_LE:  return "le";
+        case ARMCC_AL:  return "al";
+        default: return "";
+    }
 }
 
-inline static char *ARM_PROC_IFlagsToString(unsigned val)
+inline static const char *ARM_PROC_IFlagsToString(unsigned val)
 {
-       switch (val) {
-               case ARM_CPSFLAG_F: return "f";
-               case ARM_CPSFLAG_I: return "i";
-               case ARM_CPSFLAG_A: return "a";
-               default: return "";
-       }
+    switch (val) {
+        case ARM_CPSFLAG_F: return "f";
+        case ARM_CPSFLAG_I: return "i";
+        case ARM_CPSFLAG_A: return "a";
+        default: return "";
+    }
 }
 
-inline static char *ARM_PROC_IModToString(unsigned val)
+inline static const char *ARM_PROC_IModToString(unsigned val)
 {
-       switch (val) {
-               case ARM_CPSMODE_IE: return "ie";
-               case ARM_CPSMODE_ID: return "id";
-               default: return "";
-       }
+    switch (val) {
+        case ARM_CPSMODE_IE: return "ie";
+        case ARM_CPSMODE_ID: return "id";
+        default: return "";
+    }
 }
 
-inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
+inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
 {
-       switch (val) {
-               default: return "BUGBUG";
-               case ARM_MB_SY:    return "sy";
-               case ARM_MB_ST:    return "st";
-               case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
-               case ARM_MB_RESERVED_12: return "#0xc";
-               case ARM_MB_ISH:   return "ish";
-               case ARM_MB_ISHST: return "ishst";
-               case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#0x9";
-               case ARM_MB_RESERVED_8: return "#0x8";
-               case ARM_MB_NSH:   return "nsh";
-               case ARM_MB_NSHST: return "nshst";
-               case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
-               case ARM_MB_RESERVED_4: return "#0x4";
-               case ARM_MB_OSH:   return "osh";
-               case ARM_MB_OSHST: return "oshst";
-               case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
-               case ARM_MB_RESERVED_0: return "#0x0";
-       }
+    switch (val) {
+        default: return "BUGBUG";
+        case ARM_MB_SY:    return "sy";
+        case ARM_MB_ST:    return "st";
+        case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
+        case ARM_MB_RESERVED_12: return "#0xc";
+        case ARM_MB_ISH:   return "ish";
+        case ARM_MB_ISHST: return "ishst";
+        case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#0x9";
+        case ARM_MB_RESERVED_8: return "#0x8";
+        case ARM_MB_NSH:   return "nsh";
+        case ARM_MB_NSHST: return "nshst";
+        case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
+        case ARM_MB_RESERVED_4: return "#0x4";
+        case ARM_MB_OSH:   return "osh";
+        case ARM_MB_OSHST: return "oshst";
+        case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
+        case ARM_MB_RESERVED_0: return "#0x0";
+    }
 }
 
 enum ARM_ISB_InstSyncBOpt {
@@ -153,41 +153,41 @@ enum ARM_ISB_InstSyncBOpt {
     ARM_ISB_SY = 15
 };
 
-inline static char *ARM_ISB_InstSyncBOptToString(unsigned val)
+inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
 {
-       switch (val) {
-               default: // never reach
-               case ARM_ISB_RESERVED_0:  return "#0x0";
-               case ARM_ISB_RESERVED_1:  return "#0x1";
-               case ARM_ISB_RESERVED_2:  return "#0x2";
-               case ARM_ISB_RESERVED_3:  return "#0x3";
-               case ARM_ISB_RESERVED_4:  return "#0x4";
-               case ARM_ISB_RESERVED_5:  return "#0x5";
-               case ARM_ISB_RESERVED_6:  return "#0x6";
-               case ARM_ISB_RESERVED_7:  return "#0x7";
-               case ARM_ISB_RESERVED_8:  return "#0x8";
-               case ARM_ISB_RESERVED_9:  return "#0x9";
-               case ARM_ISB_RESERVED_10: return "#0xa";
-               case ARM_ISB_RESERVED_11: return "#0xb";
-               case ARM_ISB_RESERVED_12: return "#0xc";
-               case ARM_ISB_RESERVED_13: return "#0xd";
-               case ARM_ISB_RESERVED_14: return "#0xe";
-               case ARM_ISB_SY:          return "sy";
-       }
+    switch (val) {
+        default: // never reach
+        case ARM_ISB_RESERVED_0:  return "#0x0";
+        case ARM_ISB_RESERVED_1:  return "#0x1";
+        case ARM_ISB_RESERVED_2:  return "#0x2";
+        case ARM_ISB_RESERVED_3:  return "#0x3";
+        case ARM_ISB_RESERVED_4:  return "#0x4";
+        case ARM_ISB_RESERVED_5:  return "#0x5";
+        case ARM_ISB_RESERVED_6:  return "#0x6";
+        case ARM_ISB_RESERVED_7:  return "#0x7";
+        case ARM_ISB_RESERVED_8:  return "#0x8";
+        case ARM_ISB_RESERVED_9:  return "#0x9";
+        case ARM_ISB_RESERVED_10: return "#0xa";
+        case ARM_ISB_RESERVED_11: return "#0xb";
+        case ARM_ISB_RESERVED_12: return "#0xc";
+        case ARM_ISB_RESERVED_13: return "#0xd";
+        case ARM_ISB_RESERVED_14: return "#0xe";
+        case ARM_ISB_SY:          return "sy";
+    }
 }
 
 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
 ///
 static inline bool isARMLowRegister(unsigned Reg)
 {
-       //using namespace ARM;
-       switch (Reg) {
-               case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
-               case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
-                       return true;
-               default:
-                       return false;
-       }
+    //using namespace ARM;
+    switch (Reg) {
+        case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
+        case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
+            return true;
+        default:
+            return false;
+    }
 }
 
 /// ARMII - This namespace holds all of the target specific flags that
@@ -195,238 +195,238 @@ static inline bool isARMLowRegister(unsigned Reg)
 ///
 /// ARM Index Modes
 enum ARMII_IndexMode {
-       ARMII_IndexModeNone  = 0,
-       ARMII_IndexModePre   = 1,
-       ARMII_IndexModePost  = 2,
-       ARMII_IndexModeUpd   = 3
+    ARMII_IndexModeNone  = 0,
+    ARMII_IndexModePre   = 1,
+    ARMII_IndexModePost  = 2,
+    ARMII_IndexModeUpd   = 3
 };
 
 /// ARM Addressing Modes
 typedef enum ARMII_AddrMode {
-       ARMII_AddrModeNone    = 0,
-       ARMII_AddrMode1       = 1,
-       ARMII_AddrMode2       = 2,
-       ARMII_AddrMode3       = 3,
-       ARMII_AddrMode4       = 4,
-       ARMII_AddrMode5       = 5,
-       ARMII_AddrMode6       = 6,
-       ARMII_AddrModeT1_1    = 7,
-       ARMII_AddrModeT1_2    = 8,
-       ARMII_AddrModeT1_4    = 9,
-       ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
-       ARMII_AddrModeT2_i12  = 11,
-       ARMII_AddrModeT2_i8   = 12,
-       ARMII_AddrModeT2_so   = 13,
-       ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
-       ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
-       ARMII_AddrMode_i12    = 16
+    ARMII_AddrModeNone    = 0,
+    ARMII_AddrMode1       = 1,
+    ARMII_AddrMode2       = 2,
+    ARMII_AddrMode3       = 3,
+    ARMII_AddrMode4       = 4,
+    ARMII_AddrMode5       = 5,
+    ARMII_AddrMode6       = 6,
+    ARMII_AddrModeT1_1    = 7,
+    ARMII_AddrModeT1_2    = 8,
+    ARMII_AddrModeT1_4    = 9,
+    ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
+    ARMII_AddrModeT2_i12  = 11,
+    ARMII_AddrModeT2_i8   = 12,
+    ARMII_AddrModeT2_so   = 13,
+    ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
+    ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
+    ARMII_AddrMode_i12    = 16
 } ARMII_AddrMode;
 
-inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
+inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
 {
-       switch (addrmode) {
-               case ARMII_AddrModeNone:    return "AddrModeNone";
-               case ARMII_AddrMode1:       return "AddrMode1";
-               case ARMII_AddrMode2:       return "AddrMode2";
-               case ARMII_AddrMode3:       return "AddrMode3";
-               case ARMII_AddrMode4:       return "AddrMode4";
-               case ARMII_AddrMode5:       return "AddrMode5";
-               case ARMII_AddrMode6:       return "AddrMode6";
-               case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
-               case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
-               case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
-               case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
-               case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
-               case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
-               case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
-               case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
-               case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
-               case ARMII_AddrMode_i12:    return "AddrMode_i12";
-       }
+    switch (addrmode) {
+        case ARMII_AddrModeNone:    return "AddrModeNone";
+        case ARMII_AddrMode1:       return "AddrMode1";
+        case ARMII_AddrMode2:       return "AddrMode2";
+        case ARMII_AddrMode3:       return "AddrMode3";
+        case ARMII_AddrMode4:       return "AddrMode4";
+        case ARMII_AddrMode5:       return "AddrMode5";
+        case ARMII_AddrMode6:       return "AddrMode6";
+        case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
+        case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
+        case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
+        case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
+        case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
+        case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
+        case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
+        case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
+        case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
+        case ARMII_AddrMode_i12:    return "AddrMode_i12";
+    }
 }
 
 /// Target Operand Flag enum.
 enum ARMII_TOF {
-       //===------------------------------------------------------------------===//
-       // ARM Specific MachineOperand flags.
-
-       ARMII_MO_NO_FLAG,
-
-       /// MO_LO16 - On a symbol operand, this represents a relocation containing
-       /// lower 16 bit of the address. Used only via movw instruction.
-       ARMII_MO_LO16,
-
-       /// MO_HI16 - On a symbol operand, this represents a relocation containing
-       /// higher 16 bit of the address. Used only via movt instruction.
-       ARMII_MO_HI16,
-
-       /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
-       /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
-       /// i.e. "FOO$non_lazy_ptr".
-       /// Used only via movw instruction.
-       ARMII_MO_LO16_NONLAZY,
-
-       /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
-       /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
-       /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
-       ARMII_MO_HI16_NONLAZY,
-
-       /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
-       /// relocation containing lower 16 bit of the PC relative address of the
-       /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
-       /// Used only via movw instruction.
-       ARMII_MO_LO16_NONLAZY_PIC,
-
-       /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
-       /// relocation containing lower 16 bit of the PC relative address of the
-       /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
-       /// Used only via movt instruction.
-       ARMII_MO_HI16_NONLAZY_PIC,
-
-       /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
-       /// call operand.
-       ARMII_MO_PLT
+    //===------------------------------------------------------------------===//
+    // ARM Specific MachineOperand flags.
+
+    ARMII_MO_NO_FLAG,
+
+    /// MO_LO16 - On a symbol operand, this represents a relocation containing
+    /// lower 16 bit of the address. Used only via movw instruction.
+    ARMII_MO_LO16,
+
+    /// MO_HI16 - On a symbol operand, this represents a relocation containing
+    /// higher 16 bit of the address. Used only via movt instruction.
+    ARMII_MO_HI16,
+
+    /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
+    /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+    /// i.e. "FOO$non_lazy_ptr".
+    /// Used only via movw instruction.
+    ARMII_MO_LO16_NONLAZY,
+
+    /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
+    /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+    /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
+    ARMII_MO_HI16_NONLAZY,
+
+    /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+    /// relocation containing lower 16 bit of the PC relative address of the
+    /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+    /// Used only via movw instruction.
+    ARMII_MO_LO16_NONLAZY_PIC,
+
+    /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+    /// relocation containing lower 16 bit of the PC relative address of the
+    /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+    /// Used only via movt instruction.
+    ARMII_MO_HI16_NONLAZY_PIC,
+
+    /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
+    /// call operand.
+    ARMII_MO_PLT
 };
 
 enum {
-       //===------------------------------------------------------------------===//
-       // Instruction Flags.
-
-       //===------------------------------------------------------------------===//
-       // This four-bit field describes the addressing mode used.
-       ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
-
-       // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
-       // and store ops only.  Generic "updating" flag is used for ld/st multiple.
-       // The index mode enums are declared in ARMBaseInfo.h
-       ARMII_IndexModeShift = 5,
-       ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
-
-       //===------------------------------------------------------------------===//
-       // Instruction encoding formats.
-       //
-       ARMII_FormShift     = 7,
-       ARMII_FormMask      = 0x3f << ARMII_FormShift,
-
-       // Pseudo instructions
-       ARMII_Pseudo        = 0  << ARMII_FormShift,
-
-       // Multiply instructions
-       ARMII_MulFrm        = 1  << ARMII_FormShift,
-
-       // Branch instructions
-       ARMII_BrFrm         = 2  << ARMII_FormShift,
-       ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
-
-       // Data Processing instructions
-       ARMII_DPFrm         = 4  << ARMII_FormShift,
-       ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
-
-       // Load and Store
-       ARMII_LdFrm         = 6  << ARMII_FormShift,
-       ARMII_StFrm         = 7  << ARMII_FormShift,
-       ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
-       ARMII_StMiscFrm     = 9  << ARMII_FormShift,
-       ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
-
-       ARMII_LdStExFrm     = 11 << ARMII_FormShift,
-
-       // Miscellaneous arithmetic instructions
-       ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
-       ARMII_SatFrm        = 13 << ARMII_FormShift,
-
-       // Extend instructions
-       ARMII_ExtFrm        = 14 << ARMII_FormShift,
-
-       // VFP formats
-       ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
-       ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
-       ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
-       ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
-       ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
-       ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
-       ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
-       ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
-       ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
-       ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
-
-       // Thumb format
-       ARMII_ThumbFrm      = 25 << ARMII_FormShift,
-
-       // Miscelleaneous format
-       ARMII_MiscFrm       = 26 << ARMII_FormShift,
-
-       // NEON formats
-       ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
-       ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
-       ARMII_NDupFrm       = 29 << ARMII_FormShift,
-       ARMII_NLdStFrm      = 30 << ARMII_FormShift,
-       ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
-       ARMII_N2RegFrm      = 32 << ARMII_FormShift,
-       ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
-       ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
-       ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
-       ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
-       ARMII_N3RegFrm      = 37 << ARMII_FormShift,
-       ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
-       ARMII_NVExtFrm      = 39 << ARMII_FormShift,
-       ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
-       ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
-
-       //===------------------------------------------------------------------===//
-       // Misc flags.
-
-       // UnaryDP - Indicates this is a unary data processing instruction, i.e.
-       // it doesn't have a Rn operand.
-       ARMII_UnaryDP       = 1 << 13,
-
-       // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
-       // a 16-bit Thumb instruction if certain conditions are met.
-       ARMII_Xform16Bit    = 1 << 14,
-
-       // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
-       // instruction. Used by the parser to determine whether to require the 'S'
-       // suffix on the mnemonic (when not in an IT block) or preclude it (when
-       // in an IT block).
-       ARMII_ThumbArithFlagSetting = 1 << 18,
-
-       //===------------------------------------------------------------------===//
-       // Code domain.
-       ARMII_DomainShift   = 15,
-       ARMII_DomainMask    = 7 << ARMII_DomainShift,
-       ARMII_DomainGeneral = 0 << ARMII_DomainShift,
-       ARMII_DomainVFP     = 1 << ARMII_DomainShift,
-       ARMII_DomainNEON    = 2 << ARMII_DomainShift,
-       ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
-
-       //===------------------------------------------------------------------===//
-       // Field shifts - such shifts are used to set field while generating
-       // machine instructions.
-       //
-       // FIXME: This list will need adjusting/fixing as the MC code emitter
-       // takes shape and the ARMCodeEmitter.cpp bits go away.
-       ARMII_ShiftTypeShift = 4,
-
-       ARMII_M_BitShift     = 5,
-       ARMII_ShiftImmShift  = 5,
-       ARMII_ShiftShift     = 7,
-       ARMII_N_BitShift     = 7,
-       ARMII_ImmHiShift     = 8,
-       ARMII_SoRotImmShift  = 8,
-       ARMII_RegRsShift     = 8,
-       ARMII_ExtRotImmShift = 10,
-       ARMII_RegRdLoShift   = 12,
-       ARMII_RegRdShift     = 12,
-       ARMII_RegRdHiShift   = 16,
-       ARMII_RegRnShift     = 16,
-       ARMII_S_BitShift     = 20,
-       ARMII_W_BitShift     = 21,
-       ARMII_AM3_I_BitShift = 22,
-       ARMII_D_BitShift     = 22,
-       ARMII_U_BitShift     = 23,
-       ARMII_P_BitShift     = 24,
-       ARMII_I_BitShift     = 25,
-       ARMII_CondShift      = 28
+    //===------------------------------------------------------------------===//
+    // Instruction Flags.
+
+    //===------------------------------------------------------------------===//
+    // This four-bit field describes the addressing mode used.
+    ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+
+    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
+    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
+    // The index mode enums are declared in ARMBaseInfo.h
+    ARMII_IndexModeShift = 5,
+    ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
+
+    //===------------------------------------------------------------------===//
+    // Instruction encoding formats.
+    //
+    ARMII_FormShift     = 7,
+    ARMII_FormMask      = 0x3f << ARMII_FormShift,
+
+    // Pseudo instructions
+    ARMII_Pseudo        = 0  << ARMII_FormShift,
+
+    // Multiply instructions
+    ARMII_MulFrm        = 1  << ARMII_FormShift,
+
+    // Branch instructions
+    ARMII_BrFrm         = 2  << ARMII_FormShift,
+    ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
+
+    // Data Processing instructions
+    ARMII_DPFrm         = 4  << ARMII_FormShift,
+    ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
+
+    // Load and Store
+    ARMII_LdFrm         = 6  << ARMII_FormShift,
+    ARMII_StFrm         = 7  << ARMII_FormShift,
+    ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
+    ARMII_StMiscFrm     = 9  << ARMII_FormShift,
+    ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
+
+    ARMII_LdStExFrm     = 11 << ARMII_FormShift,
+
+    // Miscellaneous arithmetic instructions
+    ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
+    ARMII_SatFrm        = 13 << ARMII_FormShift,
+
+    // Extend instructions
+    ARMII_ExtFrm        = 14 << ARMII_FormShift,
+
+    // VFP formats
+    ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
+    ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
+    ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
+    ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
+    ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
+    ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
+    ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
+    ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
+    ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
+    ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
+
+    // Thumb format
+    ARMII_ThumbFrm      = 25 << ARMII_FormShift,
+
+    // Miscelleaneous format
+    ARMII_MiscFrm       = 26 << ARMII_FormShift,
+
+    // NEON formats
+    ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
+    ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
+    ARMII_NDupFrm       = 29 << ARMII_FormShift,
+    ARMII_NLdStFrm      = 30 << ARMII_FormShift,
+    ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
+    ARMII_N2RegFrm      = 32 << ARMII_FormShift,
+    ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
+    ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
+    ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
+    ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
+    ARMII_N3RegFrm      = 37 << ARMII_FormShift,
+    ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
+    ARMII_NVExtFrm      = 39 << ARMII_FormShift,
+    ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
+    ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
+
+    //===------------------------------------------------------------------===//
+    // Misc flags.
+
+    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
+    // it doesn't have a Rn operand.
+    ARMII_UnaryDP       = 1 << 13,
+
+    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
+    // a 16-bit Thumb instruction if certain conditions are met.
+    ARMII_Xform16Bit    = 1 << 14,
+
+    // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
+    // instruction. Used by the parser to determine whether to require the 'S'
+    // suffix on the mnemonic (when not in an IT block) or preclude it (when
+    // in an IT block).
+    ARMII_ThumbArithFlagSetting = 1 << 18,
+
+    //===------------------------------------------------------------------===//
+    // Code domain.
+    ARMII_DomainShift   = 15,
+    ARMII_DomainMask    = 7 << ARMII_DomainShift,
+    ARMII_DomainGeneral = 0 << ARMII_DomainShift,
+    ARMII_DomainVFP     = 1 << ARMII_DomainShift,
+    ARMII_DomainNEON    = 2 << ARMII_DomainShift,
+    ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
+
+    //===------------------------------------------------------------------===//
+    // Field shifts - such shifts are used to set field while generating
+    // machine instructions.
+    //
+    // FIXME: This list will need adjusting/fixing as the MC code emitter
+    // takes shape and the ARMCodeEmitter.cpp bits go away.
+    ARMII_ShiftTypeShift = 4,
+
+    ARMII_M_BitShift     = 5,
+    ARMII_ShiftImmShift  = 5,
+    ARMII_ShiftShift     = 7,
+    ARMII_N_BitShift     = 7,
+    ARMII_ImmHiShift     = 8,
+    ARMII_SoRotImmShift  = 8,
+    ARMII_RegRsShift     = 8,
+    ARMII_ExtRotImmShift = 10,
+    ARMII_RegRdLoShift   = 12,
+    ARMII_RegRdShift     = 12,
+    ARMII_RegRdHiShift   = 16,
+    ARMII_RegRnShift     = 16,
+    ARMII_S_BitShift     = 20,
+    ARMII_W_BitShift     = 21,
+    ARMII_AM3_I_BitShift = 22,
+    ARMII_D_BitShift     = 22,
+    ARMII_U_BitShift     = 23,
+    ARMII_P_BitShift     = 24,
+    ARMII_I_BitShift     = 25,
+    ARMII_CondShift      = 28
 };
 
 #endif
index aeda429545e6b39986c38752f19547e5734fd2c6..4bd316853439c624c49ed097ae05a4467295c1a1 100644 (file)
 
 static bool ITStatus_push_back(ARM_ITStatus *it, char v)
 {
-       if (it->size >= sizeof(it->ITStates)) {
-               // TODO: consider warning user.
-               it->size = 0;
-       }
-       it->ITStates[it->size] = v;
-       it->size++;
+    if (it->size >= sizeof(it->ITStates)) {
+        // TODO: consider warning user.
+        it->size = 0;
+    }
+    it->ITStates[it->size] = v;
+    it->size++;
 
-       return true;
+    return true;
 }
 
 // Returns true if the current instruction is in an IT block
 static bool ITStatus_instrInITBlock(ARM_ITStatus *it)
 {
-       //return !ITStates.empty();
-       return (it->size > 0);
+    //return !ITStates.empty();
+    return (it->size > 0);
 }
 
 // Returns true if current instruction is the last instruction in an IT block
 static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it)
 {
-       return (it->size == 1);
+    return (it->size == 1);
 }
 
 // Handles the condition code status of instructions in IT blocks
@@ -72,18 +72,18 @@ static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it)
 // Returns the condition code for instruction in IT block
 static unsigned ITStatus_getITCC(ARM_ITStatus *it)
 {
-       unsigned CC = ARMCC_AL;
-       if (ITStatus_instrInITBlock(it))
-               //CC = ITStates.back();
-               CC = it->ITStates[it->size-1];
-       return CC;
+    unsigned CC = ARMCC_AL;
+    if (ITStatus_instrInITBlock(it))
+        //CC = ITStates.back();
+        CC = it->ITStates[it->size-1];
+    return CC;
 }
 
 // Advances the IT block state to the next T or E
 static void ITStatus_advanceITState(ARM_ITStatus *it)
 {
-       //ITStates.pop_back();
-       it->size--;
+    //ITStates.pop_back();
+    it->size--;
 }
 
 // Called when decoding an IT instruction. Sets the IT state for the following
@@ -91,483 +91,483 @@ static void ITStatus_advanceITState(ARM_ITStatus *it)
 // fields in the IT instruction encoding.
 static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask)
 {
-       // (3 - the number of trailing zeros) is the number of then / else.
-       unsigned CondBit0 = Firstcond & 1;
-       unsigned NumTZ = CountTrailingZeros_32(Mask);
-       unsigned char CCBits = (unsigned char)Firstcond & 0xf;
-       unsigned Pos;
-       //assert(NumTZ <= 3 && "Invalid IT mask!");
-       // push condition codes onto the stack the correct order for the pops
-       for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
-               bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
-               if (T)
-                       ITStatus_push_back(it, CCBits);
-               else
-                       ITStatus_push_back(it, CCBits ^ 1);
-       }
-       ITStatus_push_back(it, CCBits);
+    // (3 - the number of trailing zeros) is the number of then / else.
+    unsigned CondBit0 = Firstcond & 1;
+    unsigned NumTZ = CountTrailingZeros_32(Mask);
+    unsigned char CCBits = (unsigned char)Firstcond & 0xf;
+    unsigned Pos;
+    //assert(NumTZ <= 3 && "Invalid IT mask!");
+    // push condition codes onto the stack the correct order for the pops
+    for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
+        bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
+        if (T)
+            ITStatus_push_back(it, CCBits);
+        else
+            ITStatus_push_back(it, CCBits ^ 1);
+    }
+    ITStatus_push_back(it, CCBits);
 }
 
 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
 
 static bool Check(DecodeStatus *Out, DecodeStatus In)
 {
-       switch (In) {
-               case MCDisassembler_Success:
-                       // Out stays the same.
-                       return true;
-               case MCDisassembler_SoftFail:
-                       *Out = In;
-                       return true;
-               case MCDisassembler_Fail:
-                       *Out = In;
-                       return false;
-               default:        // never reached
-                       return false;
-       }
+    switch (In) {
+        case MCDisassembler_Success:
+            // Out stays the same.
+            return true;
+        case MCDisassembler_SoftFail:
+            *Out = In;
+            return true;
+        case MCDisassembler_Fail:
+            *Out = In;
+            return false;
+        default:    // never reached
+            return false;
+    }
 }
 
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst,
-               unsigned RegNo, uint64_t Address, const void *Decoder);
+        unsigned RegNo, uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst,
-               unsigned RegNo, uint64_t Address, const void *Decoder);
+        unsigned RegNo, uint64_t Address, const void *Decoder);
 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst,
-               unsigned RegNo, uint64_t Address, const void *Decoder);
+        unsigned RegNo, uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
-               unsigned RegNo, uint64_t Address, const void *Decoder);
+        unsigned RegNo, uint64_t Address, const void *Decoder);
 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst,
-               unsigned Insn, uint64_t Address, const void *Decoder);
+        unsigned Insn, uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst,
-               unsigned Insn, uint64_t Adddress, const void *Decoder);
+        unsigned Insn, uint64_t Adddress, const void *Decoder);
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void* Decoder);
+        uint64_t Address, const void* Decoder);
 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void* Decoder);
+        uint64_t Address, const void* Decoder);
 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void* Decoder);
+        uint64_t Address, const void* Decoder);
 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void* Decoder);
+        uint64_t Address, const void* Decoder);
 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder);
+        uint64_t Address, const void *Decoder);
 
 // Hacky: enable all features for disassembler
 uint64_t ARM_getFeatureBits(unsigned int mode)
 {
-       uint64_t Bits = (uint64_t)-1;   // everything by default
-
-       // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
-       Bits &= (~ARM_FeatureVFPOnlySP);
-
-       // FIXME: no Armv8 support?
-       //Bits -= ARM_HasV7Ops;
-       //Bits &= ~ARM_FeatureMP;
-       if ((mode & CS_MODE_V8) == 0)
-               Bits &= ~ARM_HasV8Ops;
-       //Bits &= ~ARM_HasV6Ops;
-
-       if ((mode & CS_MODE_MCLASS) == 0)
-               Bits &= (~ARM_FeatureMClass);
-
-       // some features are mutually exclusive
-       if (mode & CS_MODE_THUMB) {
-               //Bits &= ~ARM_HasV6Ops;
-               //Bits &= ~ARM_FeatureCRC;
-               //Bits &= ~ARM_HasV5TEOps;
-               //Bits &= ~ARM_HasV4TOps;
-               //Bits &= ~ARM_HasV6T2Ops;
-               //Bits &= ~ARM_FeatureDB;
-               //Bits &= ~ARM_FeatureHWDivARM;
-               //Bits &= ~ARM_FeatureNaClTrap;
-               //Bits &= ~ARM_FeatureMClass;
-               // ArmV8
-       } else {        // ARM mode
-               Bits &= ~ARM_ModeThumb;
-               Bits &= ~ARM_FeatureThumb2;
-       }
-
-       return Bits;
+    uint64_t Bits = (uint64_t)-1;    // everything by default
+
+    // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
+    Bits &= (~ARM_FeatureVFPOnlySP);
+
+    // FIXME: no Armv8 support?
+    //Bits -= ARM_HasV7Ops;
+    //Bits &= ~ARM_FeatureMP;
+    if ((mode & CS_MODE_V8) == 0)
+        Bits &= ~ARM_HasV8Ops;
+    //Bits &= ~ARM_HasV6Ops;
+
+    if ((mode & CS_MODE_MCLASS) == 0)
+        Bits &= (~ARM_FeatureMClass);
+
+    // some features are mutually exclusive
+    if (mode & CS_MODE_THUMB) {
+        //Bits &= ~ARM_HasV6Ops;
+        //Bits &= ~ARM_FeatureCRC;
+        //Bits &= ~ARM_HasV5TEOps;
+        //Bits &= ~ARM_HasV4TOps;
+        //Bits &= ~ARM_HasV6T2Ops;
+        //Bits &= ~ARM_FeatureDB;
+        //Bits &= ~ARM_FeatureHWDivARM;
+        //Bits &= ~ARM_FeatureNaClTrap;
+        //Bits &= ~ARM_FeatureMClass;
+        // ArmV8
+    } else {    // ARM mode
+        Bits &= ~ARM_ModeThumb;
+        Bits &= ~ARM_FeatureThumb2;
+    }
+
+    return Bits;
 }
 
 #include "ARMGenDisassemblerTables.inc"
 
 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       if (Val == 0xF) return MCDisassembler_Fail;
-       // AL predicate is not allowed on Thumb1 branches.
-       if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
-               return MCDisassembler_Fail;
-       MCOperand_CreateImm0(Inst, Val);
-       if (Val == ARMCC_AL) {
-               MCOperand_CreateReg0(Inst, 0);
-       } else
-               MCOperand_CreateReg0(Inst, ARM_CPSR);
-       return MCDisassembler_Success;
+    if (Val == 0xF) return MCDisassembler_Fail;
+    // AL predicate is not allowed on Thumb1 branches.
+    if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
+        return MCDisassembler_Fail;
+    MCOperand_CreateImm0(Inst, Val);
+    if (Val == ARMCC_AL) {
+        MCOperand_CreateReg0(Inst, 0);
+    } else
+        MCOperand_CreateReg0(Inst, ARM_CPSR);
+    return MCDisassembler_Success;
 }
 
 #define GET_REGINFO_MC_DESC
 #include "ARMGenRegisterInfo.inc"
 void ARM_init(MCRegisterInfo *MRI)
 {
-       /*
-          InitMCRegisterInfo(ARMRegDesc, 289,
-          RA, PC,
-          ARMMCRegisterClasses, 100,
-          ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
-          ARMSubRegIdxLists, 57,
-          ARMSubRegIdxRanges, ARMRegEncodingTable);
-        */
+    /*
+       InitMCRegisterInfo(ARMRegDesc, 289,
+       RA, PC,
+       ARMMCRegisterClasses, 100,
+       ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
+       ARMSubRegIdxLists, 57,
+       ARMSubRegIdxRanges, ARMRegEncodingTable);
+     */
 
-       MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
-                       0, 0, 
-                       ARMMCRegisterClasses, 100,
-                       0, 0, ARMRegDiffLists, 0, 
-                       ARMSubRegIdxLists, 57,
-                       0);
+    MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
+            0, 0, 
+            ARMMCRegisterClasses, 100,
+            0, 0, ARMRegDiffLists, 0, 
+            ARMSubRegIdxLists, 57,
+            0);
 }
 
 // Post-decoding checks
 static DecodeStatus checkDecodedInstruction(MCInst *MI,
-               uint32_t Insn,
-               DecodeStatus Result)
-{
-       switch (MCInst_getOpcode(MI)) {
-               case ARM_HVC: {
-                         // HVC is undefined if condition = 0xf otherwise upredictable
-                         // if condition != 0xe
-                         uint32_t Cond = (Insn >> 28) & 0xF;
-                         if (Cond == 0xF)
-                                 return MCDisassembler_Fail;
-                         if (Cond != 0xE)
-                                 return MCDisassembler_SoftFail;
-                         return Result;
-                 }
-               default:
-                          return Result;
-       }
+        uint32_t Insn,
+        DecodeStatus Result)
+{
+    switch (MCInst_getOpcode(MI)) {
+        case ARM_HVC: {
+              // HVC is undefined if condition = 0xf otherwise upredictable
+              // if condition != 0xe
+              uint32_t Cond = (Insn >> 28) & 0xF;
+              if (Cond == 0xF)
+                  return MCDisassembler_Fail;
+              if (Cond != 0xE)
+                  return MCDisassembler_SoftFail;
+              return Result;
+          }
+        default:
+               return Result;
+    }
 }
 
 static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
-               uint16_t *Size, uint64_t Address)
-{
-       uint32_t insn, i;
-       DecodeStatus result;
-
-       if (code_len < 4)
-               // not enough data
-               return MCDisassembler_Fail;
-
-       if (MI->flat_insn->detail) {
-               memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
-               for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
-                       MI->flat_insn->detail->arm.operands[i].vector_index = -1;
-                       MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
-               }
-       }
-
-       if (ud->big_endian)
-               insn = (code[3] << 0) |
-                       (code[2] << 8) |
-                       (code[1] <<  16) |
-                       (code[0] <<  24);
-       else
-               insn = (code[3] << 24) |
-                       (code[2] << 16) |
-                       (code[1] <<  8) |
-                       (code[0] <<  0);
-
-       // Calling the auto-generated decoder function.
-       result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               result = checkDecodedInstruction(MI, insn, result);
-               if (result != MCDisassembler_Fail)
-                       *Size = 4;
-               return result;
-       }
-
-       // VFP and NEON instructions, similarly, are shared between ARM
-       // and Thumb modes.
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               // Add a fake predicate operand, because we share these instruction
-               // definitions with Thumb2 where these instructions are predicable.
-               if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-                       return MCDisassembler_Fail;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               // Add a fake predicate operand, because we share these instruction
-               // definitions with Thumb2 where these instructions are predicable.
-               if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-                       return MCDisassembler_Fail;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               // Add a fake predicate operand, because we share these instruction
-               // definitions with Thumb2 where these instructions are predicable.
-               if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-                       return MCDisassembler_Fail;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       *Size = 0;
-       return MCDisassembler_Fail;
+        uint16_t *Size, uint64_t Address)
+{
+    uint32_t insn, i;
+    DecodeStatus result;
+
+    if (code_len < 4)
+        // not enough data
+        return MCDisassembler_Fail;
+
+    if (MI->flat_insn->detail) {
+        memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
+        for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
+            MI->flat_insn->detail->arm.operands[i].vector_index = -1;
+            MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
+        }
+    }
+
+    if (MODE_IS_BIG_ENDIAN(ud->mode))
+        insn = (code[3] << 0) |
+            (code[2] << 8) |
+            (code[1] <<  16) |
+            ((uint32_t) code[0] << 24);
+    else
+        insn = ((uint32_t) code[3] << 24) |
+            (code[2] << 16) |
+            (code[1] <<  8) |
+            (code[0] <<  0);
+
+    // Calling the auto-generated decoder function.
+    result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        result = checkDecodedInstruction(MI, insn, result);
+        if (result != MCDisassembler_Fail)
+            *Size = 4;
+        return result;
+    }
+
+    // VFP and NEON instructions, similarly, are shared between ARM
+    // and Thumb modes.
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        // Add a fake predicate operand, because we share these instruction
+        // definitions with Thumb2 where these instructions are predicable.
+        if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
+            return MCDisassembler_Fail;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        // Add a fake predicate operand, because we share these instruction
+        // definitions with Thumb2 where these instructions are predicable.
+        if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
+            return MCDisassembler_Fail;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        // Add a fake predicate operand, because we share these instruction
+        // definitions with Thumb2 where these instructions are predicable.
+        if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
+            return MCDisassembler_Fail;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    *Size = 0;
+    return MCDisassembler_Fail;
 }
 
 // Thumb1 instructions don't have explicit S bits.  Rather, they
@@ -576,21 +576,21 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
 // that as a post-pass.
 static void AddThumb1SBit(MCInst *MI, bool InITBlock)
 {
-       MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-       unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
-       unsigned i;
+    const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+    unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+    unsigned i;
 
-       for (i = 0; i < NumOps; ++i) {
-               if (i == MCInst_getNumOperands(MI)) break;
-               if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) {
-                       if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue;
-                       MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
-                       return;
-               }
-       }
+    for (i = 0; i < NumOps; ++i) {
+        if (i == MCInst_getNumOperands(MI)) break;
+        if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) {
+            if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue;
+            MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
+            return;
+        }
+    }
 
-       //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
-       MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
+    //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
+    MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
 }
 
 // Most Thumb instructions don't have explicit predicates in the
@@ -599,76 +599,76 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock)
 // post-pass.
 static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
 {
-       DecodeStatus S = MCDisassembler_Success;
-       MCOperandInfo *OpInfo;
-       unsigned short NumOps;
-       unsigned int i;
-       unsigned CC;
-
-       // A few instructions actually have predicates encoded in them.  Don't
-       // try to overwrite it if we're seeing one of those.
-       switch (MCInst_getOpcode(MI)) {
-               case ARM_tBcc:
-               case ARM_t2Bcc:
-               case ARM_tCBZ:
-               case ARM_tCBNZ:
-               case ARM_tCPS:
-               case ARM_t2CPS3p:
-               case ARM_t2CPS2p:
-               case ARM_t2CPS1p:
-               case ARM_tMOVSr:
-               case ARM_tSETEND:
-                       // Some instructions (mostly conditional branches) are not
-                       // allowed in IT blocks.
-                       if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-                               S = MCDisassembler_SoftFail;
-                       else
-                               return MCDisassembler_Success;
-                       break;
-               case ARM_tB:
-               case ARM_t2B:
-               case ARM_t2TBB:
-               case ARM_t2TBH:
-                       // Some instructions (mostly unconditional branches) can
-                       // only appears at the end of, or outside of, an IT.
-                       //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
-                       if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock)))
-                               S = MCDisassembler_SoftFail;
-                       break;
-               default:
-                       break;
-       }
-
-       // If we're in an IT block, base the predicate on that.  Otherwise,
-       // assume a predicate of AL.
-       CC = ITStatus_getITCC(&(ud->ITBlock));
-       if (CC == 0xF) 
-               CC = ARMCC_AL;
-       if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-               ITStatus_advanceITState(&(ud->ITBlock));
-
-       OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-       NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
-
-       for (i = 0; i < NumOps; ++i) {
-               if (i == MCInst_getNumOperands(MI)) break;
-               if (MCOperandInfo_isPredicate(&OpInfo[i])) {
-                       MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
-                       if (CC == ARMCC_AL)
-                               MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
-                       else
-                               MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
-                       return S;
-               }
-       }
-
-       MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
-       if (CC == ARMCC_AL)
-               MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
-       else
-               MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
-
-       return S;
+    DecodeStatus S = MCDisassembler_Success;
+    const MCOperandInfo *OpInfo;
+    unsigned short NumOps;
+    unsigned int i;
+    unsigned CC;
+
+    // A few instructions actually have predicates encoded in them.  Don't
+    // try to overwrite it if we're seeing one of those.
+    switch (MCInst_getOpcode(MI)) {
+        case ARM_tBcc:
+        case ARM_t2Bcc:
+        case ARM_tCBZ:
+        case ARM_tCBNZ:
+        case ARM_tCPS:
+        case ARM_t2CPS3p:
+        case ARM_t2CPS2p:
+        case ARM_t2CPS1p:
+        case ARM_tMOVSr:
+        case ARM_tSETEND:
+            // Some instructions (mostly conditional branches) are not
+            // allowed in IT blocks.
+            if (ITStatus_instrInITBlock(&(ud->ITBlock)))
+                S = MCDisassembler_SoftFail;
+            else
+                return MCDisassembler_Success;
+            break;
+        case ARM_tB:
+        case ARM_t2B:
+        case ARM_t2TBB:
+        case ARM_t2TBH:
+            // Some instructions (mostly unconditional branches) can
+            // only appears at the end of, or outside of, an IT.
+            //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
+            if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock)))
+                S = MCDisassembler_SoftFail;
+            break;
+        default:
+            break;
+    }
+
+    // If we're in an IT block, base the predicate on that.  Otherwise,
+    // assume a predicate of AL.
+    CC = ITStatus_getITCC(&(ud->ITBlock));
+    if (CC == 0xF) 
+        CC = ARMCC_AL;
+    if (ITStatus_instrInITBlock(&(ud->ITBlock)))
+        ITStatus_advanceITState(&(ud->ITBlock));
+
+    OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+    NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+
+    for (i = 0; i < NumOps; ++i) {
+        if (i == MCInst_getNumOperands(MI)) break;
+        if (MCOperandInfo_isPredicate(&OpInfo[i])) {
+            MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
+            if (CC == ARMCC_AL)
+                MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
+            else
+                MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
+            return S;
+        }
+    }
+
+    MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
+    if (CC == ARMCC_AL)
+        MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
+    else
+        MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
+
+    return S;
 }
 
 // Thumb VFP instructions are a special case.  Because we share their
@@ -678,4535 +678,4527 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
 // context as a post-pass.
 static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
 {
-       unsigned CC;
-       unsigned short NumOps;
-       MCOperandInfo *OpInfo;
-       unsigned i;
+    unsigned CC;
+    unsigned short NumOps;
+    const MCOperandInfo *OpInfo;
+    unsigned i;
 
-       CC = ITStatus_getITCC(&(ud->ITBlock));
-       if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-               ITStatus_advanceITState(&(ud->ITBlock));
+    CC = ITStatus_getITCC(&(ud->ITBlock));
+    if (ITStatus_instrInITBlock(&(ud->ITBlock)))
+        ITStatus_advanceITState(&(ud->ITBlock));
 
-       OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-       NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+    OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+    NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
 
-       for (i = 0; i < NumOps; ++i) {
-               if (MCOperandInfo_isPredicate(&OpInfo[i])) {
-                       MCOperand_setImm(MCInst_getOperand(MI, i), CC);
-                       if (CC == ARMCC_AL)
-                               MCOperand_setReg(MCInst_getOperand(MI, i+1), 0);
-                       else
-                               MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR);
-                       return;
-               }
-       }
+    for (i = 0; i < NumOps; ++i) {
+        if (MCOperandInfo_isPredicate(&OpInfo[i])) {
+            MCOperand_setImm(MCInst_getOperand(MI, i), CC);
+            if (CC == ARMCC_AL)
+                MCOperand_setReg(MCInst_getOperand(MI, i+1), 0);
+            else
+                MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR);
+            return;
+        }
+    }
 }
 
 static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
-               uint16_t *Size, uint64_t Address)
-{
-       uint16_t insn16;
-       DecodeStatus result;
-       bool InITBlock;
-       unsigned Firstcond, Mask; 
-       uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
-       size_t i;
-
-       // We want to read exactly 2 bytes of data.
-       if (code_len < 2)
-               // not enough data
-               return MCDisassembler_Fail;
-
-       if (MI->flat_insn->detail) {
-               memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
-               for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
-                       MI->flat_insn->detail->arm.operands[i].vector_index = -1;
-                       MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
-               }
-       }
-
-       if (ud->big_endian)
-               insn16 = (code[0] << 8) | code[1];
-       else
-               insn16 = (code[1] << 8) | code[0];
-
-       result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 2;
-               Check(&result, AddThumbPredicate(ud, MI));
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode);
-       if (result) {
-               *Size = 2;
-               InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
-               Check(&result, AddThumbPredicate(ud, MI));
-               AddThumb1SBit(MI, InITBlock);
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 2;
-
-               // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
-               // the Thumb predicate.
-               if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock)))
-                       return MCDisassembler_SoftFail;
-               Check(&result, AddThumbPredicate(ud, MI));
-
-               // If we find an IT instruction, we need to parse its condition
-               // code and mask operands so that we can apply them correctly
-               // to the subsequent instructions.
-               if (MCInst_getOpcode(MI) == ARM_t2IT) {
-
-                       Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
-                       Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
-                       ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
-               }
-
-               return result;
-       }
-
-       // We want to read exactly 4 bytes of data.
-       if (code_len < 4)
-               // not enough data
-               return MCDisassembler_Fail;
-
-       if (ud->big_endian)
-               insn32 = (code[3] <<  0) |
-                       (code[2] <<  8) |
-                       (code[1] << 16) |
-                       (code[0] << 24);
-       else
-               insn32 = (code[3] <<  8) |
-                       (code[2] <<  0) |
-                       (code[1] << 24) |
-                       (code[0] << 16);
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
-               Check(&result, AddThumbPredicate(ud, MI));
-               AddThumb1SBit(MI, InITBlock);
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               Check(&result, AddThumbPredicate(ud, MI));
-               return result;
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               UpdateThumbVFPPredicate(ud, MI);
-               return result;
-       }
-
-       if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
-               MCInst_clear(MI);
-               result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
-               if (result != MCDisassembler_Fail) {
-                       *Size = 4;
-                       UpdateThumbVFPPredicate(ud, MI);
-                       return result;
-               }
-       }
-
-       MCInst_clear(MI);
-       result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
-               MCInst_clear(MI);
-               result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode);
-               if (result != MCDisassembler_Fail) {
-                       *Size = 4;
-                       Check(&result, AddThumbPredicate(ud, MI));
-                       return result;
-               }
-       }
-
-       if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
-               MCInst_clear(MI);
-               NEONLdStInsn = insn32;
-               NEONLdStInsn &= 0xF0FFFFFF;
-               NEONLdStInsn |= 0x04000000;
-               result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode);
-               if (result != MCDisassembler_Fail) {
-                       *Size = 4;
-                       Check(&result, AddThumbPredicate(ud, MI));
-                       return result;
-               }
-       }
-
-       if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
-               MCInst_clear(MI);
-               NEONDataInsn = insn32;
-               NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
-               NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
-               NEONDataInsn |= 0x12000000; // Set bits 28 and 25
-               result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode);
-               if (result != MCDisassembler_Fail) {
-                       *Size = 4;
-                       Check(&result, AddThumbPredicate(ud, MI));
-                       return result;
-               }
-       }
-
-       MCInst_clear(MI);
-       NEONCryptoInsn = insn32;
-       NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
-       NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
-       NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
-       result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
-                       Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       NEONv8Insn = insn32;
-       NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
-       result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode);
-       if (result != MCDisassembler_Fail) {
-               *Size = 4;
-               return result;
-       }
-
-       MCInst_clear(MI);
-       *Size = 0;
-       return MCDisassembler_Fail;
+        uint16_t *Size, uint64_t Address)
+{
+    uint16_t insn16;
+    DecodeStatus result;
+    bool InITBlock;
+    unsigned Firstcond, Mask; 
+    uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
+    size_t i;
+
+    // We want to read exactly 2 bytes of data.
+    if (code_len < 2)
+        // not enough data
+        return MCDisassembler_Fail;
+
+    if (MI->flat_insn->detail) {
+        memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
+        for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
+            MI->flat_insn->detail->arm.operands[i].vector_index = -1;
+            MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
+        }
+    }
+
+    if (MODE_IS_BIG_ENDIAN(ud->mode))
+        insn16 = (code[0] << 8) | code[1];
+    else
+        insn16 = (code[1] << 8) | code[0];
+
+    result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 2;
+        Check(&result, AddThumbPredicate(ud, MI));
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode);
+    if (result) {
+        *Size = 2;
+        InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
+        Check(&result, AddThumbPredicate(ud, MI));
+        AddThumb1SBit(MI, InITBlock);
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 2;
+
+        // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
+        // the Thumb predicate.
+        if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock)))
+            return MCDisassembler_SoftFail;
+        Check(&result, AddThumbPredicate(ud, MI));
+
+        // If we find an IT instruction, we need to parse its condition
+        // code and mask operands so that we can apply them correctly
+        // to the subsequent instructions.
+        if (MCInst_getOpcode(MI) == ARM_t2IT) {
+
+            Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
+            Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
+            ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
+        }
+
+        return result;
+    }
+
+    // We want to read exactly 4 bytes of data.
+    if (code_len < 4)
+        // not enough data
+        return MCDisassembler_Fail;
+
+    if (MODE_IS_BIG_ENDIAN(ud->mode))
+        insn32 = (code[3] <<  0) |
+            (code[2] <<  8) |
+            (code[1] << 16) |
+            ((uint32_t) code[0] << 24);
+    else
+        insn32 = (code[3] <<  8) |
+            (code[2] <<  0) |
+            ((uint32_t) code[1] << 24) |
+            (code[0] << 16);
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
+        Check(&result, AddThumbPredicate(ud, MI));
+        AddThumb1SBit(MI, InITBlock);
+        return result;
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        Check(&result, AddThumbPredicate(ud, MI));
+        return result;
+    }
+
+    if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
+        MCInst_clear(MI);
+        result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
+        if (result != MCDisassembler_Fail) {
+            *Size = 4;
+            UpdateThumbVFPPredicate(ud, MI);
+            return result;
+        }
+    }
+
+    MCInst_clear(MI);
+    result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
+        MCInst_clear(MI);
+        result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode);
+        if (result != MCDisassembler_Fail) {
+            *Size = 4;
+            Check(&result, AddThumbPredicate(ud, MI));
+            return result;
+        }
+    }
+
+    if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
+        MCInst_clear(MI);
+        NEONLdStInsn = insn32;
+        NEONLdStInsn &= 0xF0FFFFFF;
+        NEONLdStInsn |= 0x04000000;
+        result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode);
+        if (result != MCDisassembler_Fail) {
+            *Size = 4;
+            Check(&result, AddThumbPredicate(ud, MI));
+            return result;
+        }
+    }
+
+    if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
+        MCInst_clear(MI);
+        NEONDataInsn = insn32;
+        NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
+        NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+        NEONDataInsn |= 0x12000000; // Set bits 28 and 25
+        result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode);
+        if (result != MCDisassembler_Fail) {
+            *Size = 4;
+            Check(&result, AddThumbPredicate(ud, MI));
+            return result;
+        }
+    }
+
+    MCInst_clear(MI);
+    NEONCryptoInsn = insn32;
+    NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
+    NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+    NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
+    result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
+            Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    NEONv8Insn = insn32;
+    NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
+    result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode);
+    if (result != MCDisassembler_Fail) {
+        *Size = 4;
+        return result;
+    }
+
+    MCInst_clear(MI);
+    *Size = 0;
+    return MCDisassembler_Fail;
 }
 
 bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
-               uint16_t *size, uint64_t address, void *info)
+        uint16_t *size, uint64_t address, void *info)
 {
-       DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
+    DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
 
-       //return status == MCDisassembler_Success;
-       return status != MCDisassembler_Fail;
+    //return status == MCDisassembler_Success;
+    return status != MCDisassembler_Fail;
 }
 
 bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
-               uint16_t *size, uint64_t address, void *info)
+        uint16_t *size, uint64_t address, void *info)
 {
-       DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
+    DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
 
-       //return status == MCDisassembler_Success;
-       return status != MCDisassembler_Fail;
+    //return status == MCDisassembler_Success;
+    return status != MCDisassembler_Fail;
 }
 
 static const uint16_t GPRDecoderTable[] = {
-       ARM_R0, ARM_R1, ARM_R2, ARM_R3,
-       ARM_R4, ARM_R5, ARM_R6, ARM_R7,
-       ARM_R8, ARM_R9, ARM_R10, ARM_R11,
-       ARM_R12, ARM_SP, ARM_LR, ARM_PC
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3,
+    ARM_R4, ARM_R5, ARM_R6, ARM_R7,
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11,
+    ARM_R12, ARM_SP, ARM_LR, ARM_PC
 };
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       unsigned Register;
-       if (RegNo > 15)
-               return MCDisassembler_Fail;
+    unsigned Register;
+    if (RegNo > 15)
+        return MCDisassembler_Fail;
 
-       Register = GPRDecoderTable[RegNo];
-       MCOperand_CreateReg0(Inst, Register);
-       return MCDisassembler_Success;
+    Register = GPRDecoderTable[RegNo];
+    MCOperand_CreateReg0(Inst, Register);
+    return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       DecodeStatus S = MCDisassembler_Success;
+    DecodeStatus S = MCDisassembler_Success;
 
-       if (RegNo == 15) 
-               S = MCDisassembler_SoftFail;
+    if (RegNo == 15) 
+        S = MCDisassembler_SoftFail;
 
-       Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+    Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
 
-       return S;
+    return S;
 }
 
 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       DecodeStatus S = MCDisassembler_Success;
+    DecodeStatus S = MCDisassembler_Success;
 
-       if (RegNo == 15) {
-               MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
-               return MCDisassembler_Success;
-       }
+    if (RegNo == 15) {
+        MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
+        return MCDisassembler_Success;
+    }
 
-       Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
-       return S;
+    Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+    return S;
 }
 
 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       if (RegNo > 7)
-               return MCDisassembler_Fail;
-       return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
+    if (RegNo > 7)
+        return MCDisassembler_Fail;
+    return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t GPRPairDecoderTable[] = {
-       ARM_R0_R1, ARM_R2_R3,   ARM_R4_R5,  ARM_R6_R7,
-       ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
+    ARM_R0_R1, ARM_R2_R3,   ARM_R4_R5,  ARM_R6_R7,
+    ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
 };
 
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
+        uint64_t Address, const void *Decoder)
 {
-       unsigned RegisterPair;
-       DecodeStatus S = MCDisassembler_Success;
+    unsigned RegisterPair;
+    DecodeStatus S = MCDisassembler_Success;
 
-       if (RegNo > 13)
-               return MCDisassembler_Fail;
+    if (RegNo > 13)
+        return MCDisassembler_Fail;
 
-       if ((RegNo & 1) || RegNo == 0xe)
-               S = MCDisassembler_SoftFail;
+    if ((RegNo & 1) || RegNo == 0xe)
+        S = MCDisassembler_SoftFail;
 
-       RegisterPair = GPRPairDecoderTable[RegNo/2];
-       MCOperand_CreateReg0(Inst, RegisterPair);
-       return S;
+    RegisterPair = GPRPairDecoderTable[RegNo/2];
+    MCOperand_CreateReg0(Inst, RegisterPair);
+    return S;
 }
 
 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-               uint64_t Address, const void *Decoder)
-{
-       unsigned Register = 0;
-       switch (RegNo) {
-               case 0:
-                       Register = ARM_R0;
-                       break;
-               case 1:
-                       Register = ARM_R1;
-                       break;
-               case 2:
-