Refactoring of architectural Register Information
authorcommit-queue@webkit.org <commit-queue@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Wed, 3 Jul 2019 19:52:42 +0000 (19:52 +0000)
committercommit-queue@webkit.org <commit-queue@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Wed, 3 Jul 2019 19:52:42 +0000 (19:52 +0000)
https://bugs.webkit.org/show_bug.cgi?id=198604

Patch by Paulo Matos <pmatos@igalia.com> on 2019-07-03
Reviewed by Keith Miller.

The goal of this patch is to centralize the register information per platform
but access it in a platform independent way. The patch as been implemented for all
known platforms: ARM64, ARMv7, MIPS, X86 and X86_64. Register information has
been centralized in an architecture per-file: each file is called assembler/<arch>Registers.h.

RegisterInfo.h is used as a forwarding header to choose which register information to load.
assembler/<arch>Assembler.h and jit/RegisterSet.cpp use this information in a platform
independent way.

* CMakeLists.txt:
* JavaScriptCore.xcodeproj/project.pbxproj:
* assembler/ARM64Assembler.h:
(JSC::ARM64Assembler::gprName): Use register names from register info file.
(JSC::ARM64Assembler::sprName): likewise.
(JSC::ARM64Assembler::fprName): likewise.
* assembler/ARM64Registers.h: Added.
* assembler/ARMv7Assembler.h:
(JSC::ARMv7Assembler::gprName): Use register names from register info file.
(JSC::ARMv7Assembler::sprName): likewise.
(JSC::ARMv7Assembler::fprName): likewise.
* assembler/ARMv7Registers.h: Added.
* assembler/MIPSAssembler.h:
(JSC::MIPSAssembler::gprName): Use register names from register info file.
(JSC::MIPSAssembler::sprName): likewise.
(JSC::MIPSAssembler::fprName): likewise.
* assembler/MIPSRegisters.h: Added.
* assembler/RegisterInfo.h: Added.
* assembler/X86Assembler.h:
(JSC::X86Assembler::gprName): Use register names from register info file.
(JSC::X86Assembler::sprName): likewise.
(JSC::X86Assembler::fprName): likewise.
* assembler/X86Registers.h: Added.
* assembler/X86_64Registers.h: Added.
* jit/GPRInfo.h: Fix typo in comment (s/basline/baseline).
* jit/RegisterSet.cpp:
(JSC::RegisterSet::reservedHardwareRegisters): Use register properties from register info file.
(JSC::RegisterSet::calleeSaveRegisters): likewise.

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@247097 268f45cc-cd09-0410-ab3c-d52691b4dbfc

15 files changed:
Source/JavaScriptCore/CMakeLists.txt
Source/JavaScriptCore/ChangeLog
Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj
Source/JavaScriptCore/assembler/ARM64Assembler.h
Source/JavaScriptCore/assembler/ARM64Registers.h [new file with mode: 0644]
Source/JavaScriptCore/assembler/ARMv7Assembler.h
Source/JavaScriptCore/assembler/ARMv7Registers.h [new file with mode: 0644]
Source/JavaScriptCore/assembler/MIPSAssembler.h
Source/JavaScriptCore/assembler/MIPSRegisters.h [new file with mode: 0644]
Source/JavaScriptCore/assembler/RegisterInfo.h [new file with mode: 0644]
Source/JavaScriptCore/assembler/X86Assembler.h
Source/JavaScriptCore/assembler/X86Registers.h [new file with mode: 0644]
Source/JavaScriptCore/assembler/X86_64Registers.h [new file with mode: 0644]
Source/JavaScriptCore/jit/GPRInfo.h
Source/JavaScriptCore/jit/RegisterSet.cpp

index 91c4c75..e43bb6b 100644 (file)
@@ -436,7 +436,9 @@ set(JavaScriptCore_PRIVATE_FRAMEWORK_HEADERS
     API/OpaqueJSString.h
 
     assembler/ARM64Assembler.h
+    assembler/ARM64Registers.h
     assembler/ARMv7Assembler.h
+    assembler/ARMv7Registers.h
     assembler/AbortReason.h
     assembler/AbstractMacroAssembler.h
     assembler/AssemblerBuffer.h
@@ -446,6 +448,7 @@ set(JavaScriptCore_PRIVATE_FRAMEWORK_HEADERS
     assembler/CodeLocation.h
     assembler/LinkBuffer.h
     assembler/MIPSAssembler.h
+    assembler/MIPSRegisters.h
     assembler/MacroAssembler.h
     assembler/MacroAssemblerARM64.h
     assembler/MacroAssemblerARMv7.h
@@ -456,7 +459,10 @@ set(JavaScriptCore_PRIVATE_FRAMEWORK_HEADERS
     assembler/MacroAssemblerX86Common.h
     assembler/MacroAssemblerX86_64.h
     assembler/Printer.h
+    assembler/RegisterInfo.h
     assembler/X86Assembler.h
+    assembler/X86Registers.h
+    assembler/X86_64Registers.h
 
     bindings/ScriptFunctionCall.h
     bindings/ScriptObject.h
index 41d8d9a..22da981 100644 (file)
@@ -1,3 +1,48 @@
+2019-07-03  Paulo Matos  <pmatos@igalia.com>
+
+        Refactoring of architectural Register Information
+        https://bugs.webkit.org/show_bug.cgi?id=198604
+
+        Reviewed by Keith Miller.
+
+        The goal of this patch is to centralize the register information per platform
+        but access it in a platform independent way. The patch as been implemented for all
+        known platforms: ARM64, ARMv7, MIPS, X86 and X86_64. Register information has
+        been centralized in an architecture per-file: each file is called assembler/<arch>Registers.h.
+
+        RegisterInfo.h is used as a forwarding header to choose which register information to load.
+        assembler/<arch>Assembler.h and jit/RegisterSet.cpp use this information in a platform
+        independent way.
+
+        * CMakeLists.txt:
+        * JavaScriptCore.xcodeproj/project.pbxproj:
+        * assembler/ARM64Assembler.h:
+        (JSC::ARM64Assembler::gprName): Use register names from register info file.
+        (JSC::ARM64Assembler::sprName): likewise.
+        (JSC::ARM64Assembler::fprName): likewise.
+        * assembler/ARM64Registers.h: Added.
+        * assembler/ARMv7Assembler.h:
+        (JSC::ARMv7Assembler::gprName): Use register names from register info file.
+        (JSC::ARMv7Assembler::sprName): likewise.
+        (JSC::ARMv7Assembler::fprName): likewise.
+        * assembler/ARMv7Registers.h: Added.
+        * assembler/MIPSAssembler.h:
+        (JSC::MIPSAssembler::gprName): Use register names from register info file.
+        (JSC::MIPSAssembler::sprName): likewise.
+        (JSC::MIPSAssembler::fprName): likewise.
+        * assembler/MIPSRegisters.h: Added.
+        * assembler/RegisterInfo.h: Added.
+        * assembler/X86Assembler.h:
+        (JSC::X86Assembler::gprName): Use register names from register info file.
+        (JSC::X86Assembler::sprName): likewise.
+        (JSC::X86Assembler::fprName): likewise.
+        * assembler/X86Registers.h: Added.
+        * assembler/X86_64Registers.h: Added.
+        * jit/GPRInfo.h: Fix typo in comment (s/basline/baseline).
+        * jit/RegisterSet.cpp:
+        (JSC::RegisterSet::reservedHardwareRegisters): Use register properties from register info file.
+        (JSC::RegisterSet::calleeSaveRegisters): likewise.
+
 2019-07-02  Michael Saboff  <msaboff@apple.com>
 
         Exception from For..of loop destructured assignment eliminates TDZ checks in subsequent code
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                969A07200ED1CE3300F1F681 /* BytecodeGenerator.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = BytecodeGenerator.cpp; sourceTree = "<group>"; };
                969A07210ED1CE3300F1F681 /* BytecodeGenerator.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = BytecodeGenerator.h; sourceTree = "<group>"; };
                969A07270ED1CE6900F1F681 /* Label.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Label.h; sourceTree = "<group>"; };
                                AD412B351E7B57C0008AF157 /* AllowMacroScratchRegisterUsageIf.h */,
                                8640923B156EED3B00566CB2 /* ARM64Assembler.h */,
                                FE1E2C3D2240D2F600F6B729 /* ARM64EAssembler.h */,
+                               8640923B156EED3B00566CC2 /* ARM64Registers.h */,
                                86ADD1430FDDEA980006EEC2 /* ARMv7Assembler.h */,
+                               86ADD1430FDDEA980006FFCC /* ARMv7Registers.h */,
                                9688CB130ED12B4E001D649F /* AssemblerBuffer.h */,
                                86D3B2C110156BDE002865E7 /* AssemblerBufferWithConstantPool.h */,
                                43C392AA1C3BEB0000241F53 /* AssemblerCommon.h */,
                                860161E20F3A83C100F84710 /* MacroAssemblerX86Common.h */,
                                65860177185A8F5E00030EEE /* MaxFrameExtentForSlowPathCall.h */,
                                86C568DF11A213EE0007F7F0 /* MIPSAssembler.h */,
+                               86C568DF11A213EE0007F7FF /* MIPSRegisters.h */,
                                FE63DD551EA9BC5D00103A69 /* Printer.cpp */,
                                FE63DD531EA9B60E00103A69 /* Printer.h */,
                                FE10AAF31F46826D009DEDC5 /* ProbeContext.cpp */,
                                FEB41CCB1F73284200C5481E /* ProbeFrame.h */,
                                FE10AAE91F44D510009DEDC5 /* ProbeStack.cpp */,
                                FE10AAEA1F44D512009DEDC5 /* ProbeStack.h */,
+                               9688CB140ED12B4E001D6499 /* RegisterInfo.h */,
                                FE533CA01F217C310016A1FE /* testmasm.cpp */,
                                9688CB140ED12B4E001D649F /* X86Assembler.h */,
+                               9688CB140ED12B4E001D6491 /* X86Registers.h */,
+                               9688CB140ED12B4E001D6492 /* X86_64Registers.h */,
                        );
                        path = assembler;
                        sourceTree = "<group>";
                                0F6B1CB91861244C00845D97 /* ArityCheckMode.h in Headers */,
                                A1A009C11831A26E00CF8711 /* ARM64Assembler.h in Headers */,
                                FE1E2C402240DD6200F6B729 /* ARM64EAssembler.h in Headers */,
+                               A1A009C11831A26E00CF8722 /* ARM64Registers.h */,
                                86ADD1450FDDEA980006EEC2 /* ARMv7Assembler.h in Headers */,
+                               86ADD1450FDDEA980006FFCC /* ARMv7Registers.h in Headers */,
                                0F8335B81639C1EA001443B5 /* ArrayAllocationProfile.h in Headers */,
                                A7A8AF3517ADB5F3005AB174 /* ArrayBuffer.h in Headers */,
                                0FFC99D5184EE318009C10AB /* ArrayBufferNeuteringWatchpointSet.h in Headers */,
                                7C008CE7187631B600955C24 /* Microtask.h in Headers */,
                                FE2A87601F02381600EB31B2 /* MinimumReservedZoneSize.h in Headers */,
                                86C568E211A213EE0007F7F0 /* MIPSAssembler.h in Headers */,
+                               86C568E211A213EE0007F7FF /* MIPSRegisters.h in Headers */,
                                C4703CD7192844CC0013FBEA /* models.py in Headers */,
                                E3794E761B77EB97005543AE /* ModuleAnalyzer.h in Headers */,
                                9F63434577274FAFB9336C38 /* ModuleNamespaceAccessCase.h in Headers */,
                                E328C6C91DA432F900D255FD /* RegisterAtOffset.h in Headers */,
                                E328C6C81DA4306100D255FD /* RegisterAtOffsetList.h in Headers */,
                                969A072B0ED1CE6900F1F681 /* RegisterID.h in Headers */,
+                               9688CB160ED12B4E001D6499 /* RegisterInfo.h in Headers */,
                                623A37EC1B87A7C000754209 /* RegisterMap.h in Headers */,
                                0FC314121814559100033232 /* RegisterSet.h in Headers */,
                                0FD0E5F01E46BF250006AB08 /* RegisterState.h in Headers */,
                                C2B6D75318A33793004A9301 /* WriteBarrierInlines.h in Headers */,
                                0FC8150A14043BF500CFA603 /* WriteBarrierSupport.h in Headers */,
                                9688CB160ED12B4E001D649F /* X86Assembler.h in Headers */,
+                               9688CB160ED12B4E001D6491 /* X86Registers.h in Headers */,
+                               9688CB160ED12B4E001D6492 /* X86_64Registers.h in Headers */,
                                9959E92E1BD17FA4001AA413 /* xxd.pl in Headers */,
                                451539B912DC994500EF7AC4 /* Yarr.h in Headers */,
                                E3282BBB1FE930AF00EDAF71 /* YarrErrorCode.h in Headers */,
index 544b612..447b844 100644 (file)
@@ -27,6 +27,7 @@
 
 #if ENABLE(ASSEMBLER) && CPU(ARM64)
 
+#include "ARM64Registers.h"
 #include "AssemblerBuffer.h"
 #include "AssemblerCommon.h"
 #include "CPU.h"
@@ -164,102 +165,33 @@ inline uint16_t getHalfword(uint64_t value, int which)
     return value >> (which << 4);
 }
 
-namespace ARM64Registers {
+namespace RegisterNames {
 
 typedef enum : int8_t {
-    // Parameter/result registers.
-    x0,
-    x1,
-    x2,
-    x3,
-    x4,
-    x5,
-    x6,
-    x7,
-    // Indirect result location register.
-    x8,
-    // Temporary registers.
-    x9,
-    x10,
-    x11,
-    x12,
-    x13,
-    x14,
-    x15,
-    // Intra-procedure-call scratch registers (temporary).
-    x16,
-    x17,
-    // Platform Register (temporary).
-    x18,
-    // Callee-saved.
-    x19,
-    x20,
-    x21,
-    x22,
-    x23,
-    x24,
-    x25,
-    x26,
-    x27,
-    x28,
-    // Special.
-    fp,
-    lr,
-    sp,
-
-    ip0 = x16,
-    ip1 = x17,
-    x29 = fp,
-    x30 = lr,
-    zr = 0x3f,
+#define REGISTER_ID(id, name, r, cs) id,
+    FOR_EACH_GP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
+
+#define REGISTER_ALIAS(id, name, alias) id = alias,
+    FOR_EACH_REGISTER_ALIAS(REGISTER_ALIAS)
+#undef REGISTER_ALIAS
+
     InvalidGPRReg = -1,
 } RegisterID;
 
 typedef enum : int8_t {
-    pc,
-    nzcv,
-    fpsr
+#define REGISTER_ID(id, name) id,
+    FOR_EACH_SP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
 } SPRegisterID;
 
 // ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
 // and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
 // However, we only use them for 64-bit doubles.
 typedef enum : int8_t {
-    // Parameter/result registers.
-    q0,
-    q1,
-    q2,
-    q3,
-    q4,
-    q5,
-    q6,
-    q7,
-    // Callee-saved (up to 64-bits only!).
-    q8,
-    q9,
-    q10,
-    q11,
-    q12,
-    q13,
-    q14,
-    q15,
-    // Temporary registers.
-    q16,
-    q17,
-    q18,
-    q19,
-    q20,
-    q21,
-    q22,
-    q23,
-    q24,
-    q25,
-    q26,
-    q27,
-    q28,
-    q29,
-    q30,
-    q31,
+#define REGISTER_ID(id, name, r, cs) id,
+    FOR_EACH_FP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID                       
     InvalidFPRReg = -1,
 } FPRegisterID;
 
@@ -292,10 +224,9 @@ public:
     {
         ASSERT(id >= firstRegister() && id <= lastRegister());
         static const char* const nameForRegister[numberOfRegisters()] = {
-            "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-            "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
-            "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-            "r24", "r25", "r26", "r27", "r28", "fp", "lr", "sp"
+#define REGISTER_NAME(id, name, r, cs) name,
+        FOR_EACH_GP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
@@ -304,7 +235,9 @@ public:
     {
         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
         static const char* const nameForRegister[numberOfSPRegisters()] = {
-            "pc", "nzcv", "fpsr"
+#define REGISTER_NAME(id, name) name,
+        FOR_EACH_SP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
@@ -313,10 +246,9 @@ public:
     {
         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
         static const char* const nameForRegister[numberOfFPRegisters()] = {
-            "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
-            "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
-            "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
-            "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
+#define REGISTER_NAME(id, name, r, cs) name,
+        FOR_EACH_FP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
diff --git a/Source/JavaScriptCore/assembler/ARM64Registers.h b/Source/JavaScriptCore/assembler/ARM64Registers.h
new file mode 100644 (file)
index 0000000..a19291f
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#pragma once
+
+#include <wtf/Platform.h>
+
+#define RegisterNames ARM64Registers
+
+#define FOR_EACH_REGISTER(macro)                \
+    FOR_EACH_GP_REGISTER(macro)                 \
+    FOR_EACH_FP_REGISTER(macro)
+
+// We don't include LR in the set of callee-save registers even though it technically belongs
+// there. This is because we use this set to describe the set of registers that need to be saved
+// beyond what you would save by the platform-agnostic "preserve return address" and "restore
+// return address" operations in CCallHelpers.
+
+#if !PLATFORM(IOS_FAMILY)
+#define FOR_EACH_GP_REGISTER(macro)                             \
+    /* Parameter/result registers. */                           \
+    macro(x0,  "x0",  0, 0)                                     \
+    macro(x1,  "x1",  0, 0)                                     \
+    macro(x2,  "x2",  0, 0)                                     \
+    macro(x3,  "x3",  0, 0)                                     \
+    macro(x4,  "x4",  0, 0)                                     \
+    macro(x5,  "x5",  0, 0)                                     \
+    macro(x6,  "x6",  0, 0)                                     \
+    macro(x7,  "x7",  0, 0)                                     \
+    /* Indirect result location register. */                    \
+    macro(x8,  "x8",  0, 0)                                     \
+    /* Temporary registers. */                                  \
+    macro(x9,  "x9",  0, 0)                                     \
+    macro(x10, "x10", 0, 0)                                     \
+    macro(x11, "x11", 0, 0)                                     \
+    macro(x12, "x12", 0, 0)                                     \
+    macro(x13, "x13", 0, 0)                                     \
+    macro(x14, "x14", 0, 0)                                     \
+    macro(x15, "x15", 0, 0)                                     \
+    /* Intra-procedure-call scratch registers (temporary). */   \
+    macro(x16, "x16", 0, 0)                                     \
+    macro(x17, "x17", 0, 0)                                     \
+    /* Platform Register (temporary). */                        \
+    macro(x18, "x18", 0, 0)                                     \
+    /* Callee-saved. */                                         \
+    macro(x19, "x19", 0, 1)                                     \
+    macro(x20, "x20", 0, 1)                                     \
+    macro(x21, "x21", 0, 1)                                     \
+    macro(x22, "x22", 0, 1)                                     \
+    macro(x23, "x23", 0, 1)                                     \
+    macro(x24, "x24", 0, 1)                                     \
+    macro(x25, "x25", 0, 1)                                     \
+    macro(x26, "x26", 0, 1)                                     \
+    macro(x27, "x27", 0, 1)                                     \
+    macro(x28, "x28", 0, 1)                                     \
+    /* Special. */                                              \
+    macro(fp,  "fp",  0, 1)                                     \
+    macro(lr,  "lr",  1, 0)                                     \
+    macro(sp,  "sp",  0, 0)
+#else
+#define FOR_EACH_GP_REGISTER(macro)                             \
+    /* Parameter/result registers. */                           \
+    macro(x0,  "x0",  0, 0)                                     \
+    macro(x1,  "x1",  0, 0)                                     \
+    macro(x2,  "x2",  0, 0)                                     \
+    macro(x3,  "x3",  0, 0)                                     \
+    macro(x4,  "x4",  0, 0)                                     \
+    macro(x5,  "x5",  0, 0)                                     \
+    macro(x6,  "x6",  0, 0)                                     \
+    macro(x7,  "x7",  0, 0)                                     \
+    /* Indirect result location register. */                    \
+    macro(x8,  "x8",  0, 0)                                     \
+    /* Temporary registers. */                                  \
+    macro(x9,  "x9",  0, 0)                                     \
+    macro(x10, "x10", 0, 0)                                     \
+    macro(x11, "x11", 0, 0)                                     \
+    macro(x12, "x12", 0, 0)                                     \
+    macro(x13, "x13", 0, 0)                                     \
+    macro(x14, "x14", 0, 0)                                     \
+    macro(x15, "x15", 0, 0)                                     \
+    /* Intra-procedure-call scratch registers (temporary). */   \
+    macro(x16, "x16", 0, 0)                                     \
+    macro(x17, "x17", 0, 0)                                     \
+    /* Platform Register (temporary). */                        \
+    macro(x18, "x18", 1, 0)                                     \
+    /* Callee-saved. */                                         \
+    macro(x19, "x19", 0, 1)                                     \
+    macro(x20, "x20", 0, 1)                                     \
+    macro(x21, "x21", 0, 1)                                     \
+    macro(x22, "x22", 0, 1)                                     \
+    macro(x23, "x23", 0, 1)                                     \
+    macro(x24, "x24", 0, 1)                                     \
+    macro(x25, "x25", 0, 1)                                     \
+    macro(x26, "x26", 0, 1)                                     \
+    macro(x27, "x27", 0, 1)                                     \
+    macro(x28, "x28", 0, 1)                                     \
+    /* Special. */                                              \
+    macro(fp,  "fp",  0, 1)                                     \
+    macro(lr,  "lr",  1, 0)                                     \
+    macro(sp,  "sp",  0, 0)
+#endif
+
+#define FOR_EACH_REGISTER_ALIAS(macro)          \
+    macro(ip0, "ip0", x16)                      \
+    macro(ip1, "ip1", x17)                      \
+    macro(x29, "x29", fp)                       \
+    macro(x30, "x30", lr)                       \
+    macro(zr,  "zr",  0x3f)
+
+#define FOR_EACH_SP_REGISTER(macro)             \
+    macro(pc,   "pc")                           \
+    macro(nzcv, "nzcv")                         \
+    macro(fpsr, "fpsr")
+
+#define FOR_EACH_FP_REGISTER(macro)             \
+    /* Parameter/result registers. */           \
+    macro(q0,  "q0",  0, 0)                     \
+    macro(q1,  "q1",  0, 0)                     \
+    macro(q2,  "q2",  0, 0)                     \
+    macro(q3,  "q3",  0, 0)                     \
+    macro(q4,  "q4",  0, 0)                     \
+    macro(q5,  "q5",  0, 0)                     \
+    macro(q6,  "q6",  0, 0)                     \
+    macro(q7,  "q7",  0, 0)                     \
+    /* Callee-saved (up to 64-bits only!). */   \
+    macro(q8,  "q8",  0, 1)                     \
+    macro(q9,  "q9",  0, 1)                     \
+    macro(q10, "q10", 0, 1)                     \
+    macro(q11, "q11", 0, 1)                     \
+    macro(q12, "q12", 0, 1)                     \
+    macro(q13, "q13", 0, 1)                     \
+    macro(q14, "q14", 0, 1)                     \
+    macro(q15, "q15", 0, 1)                     \
+    /* Temporary registers. */                  \
+    macro(q16, "q16", 0, 0)                     \
+    macro(q17, "q17", 0, 0)                     \
+    macro(q18, "q18", 0, 0)                     \
+    macro(q19, "q19", 0, 0)                     \
+    macro(q20, "q20", 0, 0)                     \
+    macro(q21, "q21", 0, 0)                     \
+    macro(q22, "q22", 0, 0)                     \
+    macro(q23, "q23", 0, 0)                     \
+    macro(q24, "q24", 0, 0)                     \
+    macro(q25, "q25", 0, 0)                     \
+    macro(q26, "q26", 0, 0)                     \
+    macro(q27, "q27", 0, 0)                     \
+    macro(q28, "q28", 0, 0)                     \
+    macro(q29, "q29", 0, 0)                     \
+    macro(q30, "q30", 0, 0)                     \
+    macro(q31, "q31", 0, 0)
+
index 6fe04e4..91e73af 100644 (file)
@@ -30,6 +30,7 @@
 
 #include "AssemblerBuffer.h"
 #include "AssemblerCommon.h"
+#include "RegisterInfo.h"
 #include <limits.h>
 #include <wtf/Assertions.h>
 #include <wtf/Vector.h>
 
 namespace JSC {
 
-namespace ARMRegisters {
+namespace RegisterNames {
 
     typedef enum : int8_t {
-        r0,
-        r1,
-        r2,
-        r3,
-        r4,
-        r5,
-        r6,
-        r7,
-        r8,
-        r9,
-        r10,
-        r11,
-        r12,
-        r13,
-        r14,
-        r15,
-
-        fp = r7,   // frame pointer
-        sb = r9,   // static base
-        sl = r10,  // stack limit
-        ip = r12,
-        sp = r13,
-        lr = r14,
-        pc = r15,
+#define REGISTER_ID(id, name, r, cs) id,
+        FOR_EACH_GP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
+
+#define REGISTER_ALIAS(id, name, alias) id = alias,
+        FOR_EACH_REGISTER_ALIAS(REGISTER_ALIAS)
+#undef REGISTER_ALIAS
         InvalidGPRReg = -1,
     } RegisterID;
 
     typedef enum : int8_t {
-        apsr,
-        fpscr
+#define REGISTER_ID(id, name) id,
+        FOR_EACH_SP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
     } SPRegisterID;
 
     typedef enum : int8_t {
-        s0,
-        s1,
-        s2,
-        s3,
-        s4,
-        s5,
-        s6,
-        s7,
-        s8,
-        s9,
-        s10,
-        s11,
-        s12,
-        s13,
-        s14,
-        s15,
-        s16,
-        s17,
-        s18,
-        s19,
-        s20,
-        s21,
-        s22,
-        s23,
-        s24,
-        s25,
-        s26,
-        s27,
-        s28,
-        s29,
-        s30,
-        s31,
+#define REGISTER_ID(id, name, r, cs) id,
+        FOR_EACH_FP_SINGLE_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
     } FPSingleRegisterID;
 
     typedef enum : int8_t {
-        d0,
-        d1,
-        d2,
-        d3,
-        d4,
-        d5,
-        d6,
-        d7,
-        d8,
-        d9,
-        d10,
-        d11,
-        d12,
-        d13,
-        d14,
-        d15,
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-        d16,
-        d17,
-        d18,
-        d19,
-        d20,
-        d21,
-        d22,
-        d23,
-        d24,
-        d25,
-        d26,
-        d27,
-        d28,
-        d29,
-        d30,
-        d31,
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
+#define REGISTER_ID(id, name, r, cs) id,
+        FOR_EACH_FP_DOUBLE_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
         InvalidFPRReg = -1,
     } FPDoubleRegisterID;
 
 #if CPU(ARM_NEON)
     typedef enum : int8_t {
-        q0,
-        q1,
-        q2,
-        q3,
-        q4,
-        q5,
-        q6,
-        q7,
-        q8,
-        q9,
-        q10,
-        q11,
-        q12,
-        q13,
-        q14,
-        q15,
+#define REGISTER_ID(id, name, r, cs) id,
+        FOR_EACH_FP_QUAD_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
     } FPQuadRegisterID;
 #endif // CPU(ARM_NEON)
 
@@ -455,10 +367,9 @@ public:
     {
         ASSERT(id >= firstRegister() && id <= lastRegister());
         static const char* const nameForRegister[numberOfRegisters()] = {
-            "r0", "r1", "r2", "r3",
-            "r4", "r5", "r6", "fp",
-            "r8", "r9", "r10", "r11",
-            "ip", "sp", "lr", "pc"
+#define REGISTER_NAME(id, name, r, cs) name,
+        FOR_EACH_GP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME        
         };
         return nameForRegister[id];
     }
@@ -467,7 +378,9 @@ public:
     {
         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
         static const char* const nameForRegister[numberOfSPRegisters()] = {
-            "apsr", "fpscr"
+#define REGISTER_NAME(id, name) name,
+        FOR_EACH_SP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
@@ -476,16 +389,9 @@ public:
     {
         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
         static const char* const nameForRegister[numberOfFPRegisters()] = {
-            "d0", "d1", "d2", "d3",
-            "d4", "d5", "d6", "d7",
-            "d8", "d9", "d10", "d11",
-            "d12", "d13", "d14", "d15",
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-            "d16", "d17", "d18", "d19",
-            "d20", "d21", "d22", "d23",
-            "d24", "d25", "d26", "d27",
-            "d28", "d29", "d30", "d31"
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
+#define REGISTER_NAME(id, name, r, cs) name,
+        FOR_EACH_FP_DOUBLE_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
diff --git a/Source/JavaScriptCore/assembler/ARMv7Registers.h b/Source/JavaScriptCore/assembler/ARMv7Registers.h
new file mode 100644 (file)
index 0000000..786225a
--- /dev/null
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#pragma once
+
+#include <wtf/Platform.h>
+
+#define RegisterNames ARMRegisters
+
+#define FOR_EACH_REGISTER(macro)                \
+    FOR_EACH_GP_REGISTER(macro)                 \
+    FOR_EACH_FP_REGISTER(macro)
+
+#define FOR_EACH_FP_REGISTER(macro)             \
+    FOR_EACH_FP_DOUBLE_REGISTER(macro)
+
+#if !PLATFORM(IOS_FAMILY)
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(r0,  "r0",  0, 0)                     \
+    macro(r1,  "r1",  0, 0)                     \
+    macro(r2,  "r2",  0, 0)                     \
+    macro(r3,  "r3",  0, 0)                     \
+    macro(r4,  "r4",  0, 1)                     \
+    macro(r5,  "r5",  0, 1)                     \
+    macro(r6,  "r6",  0, 1)                     \
+    macro(r7,  "r7",  0, 0)                     \
+    macro(r8,  "r8",  0, 1)                     \
+    macro(r9,  "r9",  0, 1)                     \
+    macro(r10, "r10", 0, 1)                     \
+    macro(r11, "r11", 0, 1)                     \
+    macro(r12, "ip",  0, 0)                     \
+    macro(r13, "sp",  0, 0)                     \
+    macro(r14, "lr",  1, 0)                     \
+    macro(r15, "pc",  1, 0)
+#else
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(r0,  "r0",  0, 0)                     \
+    macro(r1,  "r1",  0, 0)                     \
+    macro(r2,  "r2",  0, 0)                     \
+    macro(r3,  "r3",  0, 0)                     \
+    macro(r4,  "r4",  0, 1)                     \
+    macro(r5,  "r5",  0, 1)                     \
+    macro(r6,  "r6",  0, 1)                     \
+    macro(r7,  "r7",  0, 0)                     \
+    macro(r8,  "r8",  0, 1)                     \
+    macro(r9,  "r9",  0, 0)                     \
+    macro(r10, "r10", 0, 1)                     \
+    macro(r11, "r11", 0, 1)                     \
+    macro(r12, "ip",  0, 0)                     \
+    macro(r13, "sp",  0, 0)                     \
+    macro(r14, "lr",  1, 0)                     \
+    macro(r15, "pc",  1, 0)
+#endif
+
+#define FOR_EACH_REGISTER_ALIAS(macro)          \
+    macro(fp, "fp", r7)                         \
+    macro(sb, "sb", r9)                         \
+    macro(sl, "sl", r10)                        \
+    macro(ip, "ip", r12)                        \
+    macro(sp, "sp", r13)                        \
+    macro(lr, "lr", r14)                        \
+    macro(pc, "pc", r15)
+
+#define FOR_EACH_SP_REGISTER(macro)             \
+    macro(apsr,  "apsr")                        \
+    macro(fpscr, "fpscr")
+
+#define FOR_EACH_FP_SINGLE_REGISTER(macro)      \
+    macro(s0,  "s0",  0, 0)                     \
+    macro(s1,  "s1",  0, 0)                     \
+    macro(s2,  "s2",  0, 0)                     \
+    macro(s3,  "s3",  0, 0)                     \
+    macro(s4,  "s4",  0, 0)                     \
+    macro(s5,  "s5",  0, 0)                     \
+    macro(s6,  "s6",  0, 0)                     \
+    macro(s7,  "s7",  0, 0)                     \
+    macro(s8,  "s8",  0, 0)                     \
+    macro(s9,  "s9",  0, 0)                     \
+    macro(s10, "s10", 0, 0)                     \
+    macro(s11, "s11", 0, 0)                     \
+    macro(s12, "s12", 0, 0)                     \
+    macro(s13, "s13", 0, 0)                     \
+    macro(s14, "s14", 0, 0)                     \
+    macro(s15, "s15", 0, 0)                     \
+    macro(s16, "s16", 0, 0)                     \
+    macro(s17, "s17", 0, 0)                     \
+    macro(s18, "s18", 0, 0)                     \
+    macro(s19, "s19", 0, 0)                     \
+    macro(s20, "s20", 0, 0)                     \
+    macro(s21, "s21", 0, 0)                     \
+    macro(s22, "s22", 0, 0)                     \
+    macro(s23, "s23", 0, 0)                     \
+    macro(s24, "s24", 0, 0)                     \
+    macro(s25, "s25", 0, 0)                     \
+    macro(s26, "s26", 0, 0)                     \
+    macro(s27, "s27", 0, 0)                     \
+    macro(s28, "s28", 0, 0)                     \
+    macro(s29, "s29", 0, 0)                     \
+    macro(s30, "s30", 0, 0)                     \
+    macro(s31, "s31", 0, 0)
+
+#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
+#define FOR_EACH_FP_DOUBLE_REGISTER(macro)      \
+    macro(d0,  "d0",  0, 0)                     \
+    macro(d1,  "d1",  0, 0)                     \
+    macro(d2,  "d2",  0, 0)                     \
+    macro(d3,  "d3",  0, 0)                     \
+    macro(d4,  "d4",  0, 0)                     \
+    macro(d5,  "d5",  0, 0)                     \
+    macro(d6,  "d6",  0, 0)                     \
+    macro(d7,  "d7",  0, 0)                     \
+    macro(d8,  "d8",  0, 0)                     \
+    macro(d9,  "d9",  0, 0)                     \
+    macro(d10, "d10", 0, 0)                     \
+    macro(d11, "d11", 0, 0)                     \
+    macro(d12, "d12", 0, 0)                     \
+    macro(d13, "d13", 0, 0)                     \
+    macro(d14, "d14", 0, 0)                     \
+    macro(d15, "d15", 0, 0)                     \
+    macro(d16, "d16", 0, 0)                     \
+    macro(d17, "d17", 0, 0)                     \
+    macro(d18, "d18", 0, 0)                     \
+    macro(d19, "d19", 0, 0)                     \
+    macro(d20, "d20", 0, 0)                     \
+    macro(d21, "d21", 0, 0)                     \
+    macro(d22, "d22", 0, 0)                     \
+    macro(d23, "d23", 0, 0)                     \
+    macro(d24, "d24", 0, 0)                     \
+    macro(d25, "d25", 0, 0)                     \
+    macro(d26, "d26", 0, 0)                     \
+    macro(d27, "d27", 0, 0)                     \
+    macro(d28, "d28", 0, 0)                     \
+    macro(d29, "d29", 0, 0)                     \
+    macro(d30, "d30", 0, 0)                     \
+    macro(d31, "d31", 0, 0)
+#else
+#define FOR_EACH_FP_DOUBLE_REGISTER(macro)      \
+    macro(d0,  "d0",  0, 0)                     \
+    macro(d1,  "d1",  0, 0)                     \
+    macro(d2,  "d2",  0, 0)                     \
+    macro(d3,  "d3",  0, 0)                     \
+    macro(d4,  "d4",  0, 0)                     \
+    macro(d5,  "d5",  0, 0)                     \
+    macro(d6,  "d6",  0, 0)                     \
+    macro(d7,  "d7",  0, 0)                     \
+    macro(d8,  "d8",  0, 0)                     \
+    macro(d9,  "d9",  0, 0)                     \
+    macro(d10, "d10", 0, 0)                     \
+    macro(d11, "d11", 0, 0)                     \
+    macro(d12, "d12", 0, 0)                     \
+    macro(d13, "d13", 0, 0)                     \
+    macro(d14, "d14", 0, 0)                     \
+    macro(d15, "d15", 0, 0)
+#endif
+
+#if CPU(ARM_NEON)
+#define FOR_EACH_FP_QUAD_REGISTER(macro)        \
+    macro(q0, "q0", 0, 0)                       \
+    macro(q1, "q1", 0, 0)                       \
+    macro(q2, "q2", 0, 0)                       \
+    macro(q3, "q3", 0, 0)                       \
+    macro(q4, "q4", 0, 0)                       \
+    macro(q5, "q5", 0, 0)                       \
+    macro(q6, "q6", 0, 0)                       \
+    macro(q7, "q7", 0, 0)                       \
+    macro(q8, "q8", 0, 0)                       \
+    macro(q9, "q9", 0, 0)                       \
+    macro(q10, "q10", 0, 0)                     \
+    macro(q11, "q11", 0, 0)                     \
+    macro(q12, "q12", 0, 0)                     \
+    macro(q13, "q13", 0, 0)                     \
+    macro(q14, "q14", 0, 0)                     \
+    macro(q15, "q15", 0, 0)
+#endif
index 7e8e213..a64e934 100644 (file)
@@ -32,6 +32,7 @@
 
 #include "AssemblerBuffer.h"
 #include "JITCompilationEffort.h"
+#include "MIPSRegisters.h"
 #include <limits.h>
 #include <wtf/Assertions.h>
 #include <wtf/SegmentedVector.h>
@@ -40,117 +41,27 @@ namespace JSC {
 
 typedef uint32_t MIPSWord;
 
-namespace MIPSRegisters {
+namespace RegisterNames {
 typedef enum : int8_t {
-    r0 = 0,
-    r1,
-    r2,
-    r3,
-    r4,
-    r5,
-    r6,
-    r7,
-    r8,
-    r9,
-    r10,
-    r11,
-    r12,
-    r13,
-    r14,
-    r15,
-    r16,
-    r17,
-    r18,
-    r19,
-    r20,
-    r21,
-    r22,
-    r23,
-    r24,
-    r25,
-    r26,
-    r27,
-    r28,
-    r29,
-    r30,
-    r31,
-    zero = r0,
-    at = r1,
-    v0 = r2,
-    v1 = r3,
-    a0 = r4,
-    a1 = r5,
-    a2 = r6,
-    a3 = r7,
-    t0 = r8,
-    t1 = r9,
-    t2 = r10,
-    t3 = r11,
-    t4 = r12,
-    t5 = r13,
-    t6 = r14,
-    t7 = r15,
-    s0 = r16,
-    s1 = r17,
-    s2 = r18,
-    s3 = r19,
-    s4 = r20,
-    s5 = r21,
-    s6 = r22,
-    s7 = r23,
-    t8 = r24,
-    t9 = r25,
-    k0 = r26,
-    k1 = r27,
-    gp = r28,
-    sp = r29,
-    fp = r30,
-    ra = r31,
+#define REGISTER_ID(id, name, r, cs) id,
+    FOR_EACH_GP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
+#define REGISTER_ALIAS(id, alias) id = alias,
+    FOR_EACH_REGISTER_ALIAS(REGISTER_ALIAS)
+#undef REGISTER_ALIAS
     InvalidGPRReg = -1,
 } RegisterID;
 
 typedef enum : int8_t {
-    fir = 0,
-    fccr = 25,
-    fexr = 26,
-    fenr = 28,
-    fcsr = 31,
-    pc
+#define REGISTER_ID(id, name, idx) id = idx,
+    FOR_EACH_SP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
 } SPRegisterID;
 
 typedef enum : int8_t {
-    f0,
-    f1,
-    f2,
-    f3,
-    f4,
-    f5,
-    f6,
-    f7,
-    f8,
-    f9,
-    f10,
-    f11,
-    f12,
-    f13,
-    f14,
-    f15,
-    f16,
-    f17,
-    f18,
-    f19,
-    f20,
-    f21,
-    f22,
-    f23,
-    f24,
-    f25,
-    f26,
-    f27,
-    f28,
-    f29,
-    f30,
-    f31,
+#define REGISTER_ID(id, name, r, cs) id,
+    FOR_EACH_FP_REGISTER(REGISTER_ID)
+#undef REGISTER_ID
     InvalidFPRReg = -1,
 } FPRegisterID;
 
@@ -179,46 +90,31 @@ public:
     {
         ASSERT(id >= firstRegister() && id <= lastRegister());
         static const char* const nameForRegister[numberOfRegisters()] = {
-            "zero", "at", "v0", "v1",
-            "a0", "a1", "a2", "a3",
-            "t0", "t1", "t2", "t3",
-            "t4", "t5", "t6", "t7"
+#define REGISTER_NAME(id, name, r, c) name,
+        FOR_EACH_GP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
 
     static const char* sprName(SPRegisterID id)
     {
-        switch (id) {
-        case MIPSRegisters::fir:
-            return "fir";
-        case MIPSRegisters::fccr:
-            return "fccr";
-        case MIPSRegisters::fexr:
-            return "fexr";
-        case MIPSRegisters::fenr:
-            return "fenr";
-        case MIPSRegisters::fcsr:
-            return "fcsr";
-        case MIPSRegisters::pc:
-            return "pc";
-        default:
-            RELEASE_ASSERT_NOT_REACHED();
-        }
+        ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
+        static const char* const nameForRegister[numberOfSPRegisters()] = {
+#define REGISTER_NAME(id, name, idx) name,
+        FOR_EACH_SP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
+        };
+        return nameForRegister[id];
     }
 
     static const char* fprName(FPRegisterID id)
     {
         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
         static const char* const nameForRegister[numberOfFPRegisters()] = {
-            "f0", "f1", "f2", "f3",
-            "f4", "f5", "f6", "f7",
-            "f8", "f9", "f10", "f11",
-            "f12", "f13", "f14", "f15"
-            "f16", "f17", "f18", "f19"
-            "f20", "f21", "f22", "f23"
-            "f24", "f25", "f26", "f27"
-            "f28", "f29", "f30", "f31"
+#define REGISTER_NAME(id, name, r, cs) name,
+        FOR_EACH_FP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
diff --git a/Source/JavaScriptCore/assembler/MIPSRegisters.h b/Source/JavaScriptCore/assembler/MIPSRegisters.h
new file mode 100644 (file)
index 0000000..1f1daa9
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+#pragma once
+
+#define RegisterNames MIPSRegisters
+
+#define FOR_EACH_REGISTER(macro)                \
+    FOR_EACH_GP_REGISTER(macro)                 \
+    FOR_EACH_FP_REGISTER(macro)
+
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(r0,  "zero", 0, 0)                    \
+    macro(r1,  "at",   0, 0)                    \
+    macro(r2,  "v0",   0, 0)                    \
+    macro(r3,  "v1",   0, 0)                    \
+    macro(r4,  "a0",   0, 0)                    \
+    macro(r5,  "a1",   0, 0)                    \
+    macro(r6,  "a2",   0, 0)                    \
+    macro(r7,  "a3",   0, 0)                    \
+    macro(r8,  "t0",   0, 0)                    \
+    macro(r9,  "t1",   0, 0)                    \
+    macro(r10, "t2",   0, 0)                    \
+    macro(r11, "t3",   0, 0)                    \
+    macro(r12, "t4",   0, 0)                    \
+    macro(r13, "t5",   0, 0)                    \
+    macro(r14, "t6",   0, 0)                    \
+    macro(r15, "t7",   0, 0)                    \
+    macro(r16, "s0",   0, 1)                    \
+    macro(r17, "s1",   0, 0)                    \
+    macro(r18, "s2",   0, 0)                    \
+    macro(r19, "s3",   0, 0)                    \
+    macro(r20, "s4",   0, 0)                    \
+    macro(r21, "s5",   0, 0)                    \
+    macro(r22, "s6",   0, 0)                    \
+    macro(r23, "s7",   0, 0)                    \
+    macro(r24, "t8",   0, 0)                    \
+    macro(r25, "t9",   0, 0)                    \
+    macro(r26, "k0",   0, 0)                    \
+    macro(r27, "k1",   0, 0)                    \
+    macro(r28, "gp",   0, 0)                    \
+    macro(r29, "sp",   0, 0)                    \
+    macro(r30, "fp",   0, 0)                    \
+    macro(r31, "ra",   0, 0)
+
+#define FOR_EACH_REGISTER_ALIAS(macro)          \
+    macro(zero, r0)                             \
+    macro(at,   r1)                             \
+    macro(v0,   r2)                             \
+    macro(v1,   r3)                             \
+    macro(a0,   r4)                             \
+    macro(a1,   r5)                             \
+    macro(a2,   r6)                             \
+    macro(a3,   r7)                             \
+    macro(t0,   r8)                             \
+    macro(t1,   r9)                             \
+    macro(t2,   r10)                            \
+    macro(t3,   r11)                            \
+    macro(t4,   r12)                            \
+    macro(t5,   r13)                            \
+    macro(t6,   r14)                            \
+    macro(t7,   r15)                            \
+    macro(s0,   r16)                            \
+    macro(s1,   r17)                            \
+    macro(s2,   r18)                            \
+    macro(s3,   r19)                            \
+    macro(s4,   r20)                            \
+    macro(s5,   r21)                            \
+    macro(s6,   r22)                            \
+    macro(s7,   r23)                            \
+    macro(t8,   r24)                            \
+    macro(t9,   r25)                            \
+    macro(k0,   r26)                            \
+    macro(k1,   r27)                            \
+    macro(gp,   r28)                            \
+    macro(sp,   r29)                            \
+    macro(fp,   r30)                            \
+    macro(ra,   r31)
+
+#define FOR_EACH_SP_REGISTER(macro)             \
+    macro(fir,  "fir",  0)                      \
+    macro(fccr, "fccr", 25)                     \
+    macro(fexr, "fexr", 26)                     \
+    macro(fenr, "fenr", 28)                     \
+    macro(fcsr, "fcsr", 31)                     \
+    macro(pc,   "pc",   32)
+
+#define FOR_EACH_FP_REGISTER(macro)             \
+    macro(f0,  "f0", 0, 0)                      \
+    macro(f1,  "f1", 0, 0)                      \
+    macro(f2,  "f2", 0, 0)                      \
+    macro(f3,  "f3", 0, 0)                      \
+    macro(f4,  "f4", 0, 0)                      \
+    macro(f5,  "f5", 0, 0)                      \
+    macro(f6,  "f6", 0, 0)                      \
+    macro(f7,  "f7", 0, 0)                      \
+    macro(f8,  "f8", 0, 0)                      \
+    macro(f9,  "f9", 0, 0)                      \
+    macro(f10, "f10", 0, 0)                     \
+    macro(f11, "f11", 0, 0)                     \
+    macro(f12, "f12", 0, 0)                     \
+    macro(f13, "f13", 0, 0)                     \
+    macro(f14, "f14", 0, 0)                     \
+    macro(f15, "f15", 0, 0)                     \
+    macro(f16, "f16", 0, 0)                     \
+    macro(f17, "f17", 0, 0)                     \
+    macro(f18, "f18", 0, 0)                     \
+    macro(f19, "f19", 0, 0)                     \
+    macro(f20, "f20", 0, 0)                     \
+    macro(f21, "f21", 0, 0)                     \
+    macro(f22, "f22", 0, 0)                     \
+    macro(f23, "f23", 0, 0)                     \
+    macro(f24, "f24", 0, 0)                     \
+    macro(f25, "f25", 0, 0)                     \
+    macro(f26, "f26", 0, 0)                     \
+    macro(f27, "f27", 0, 0)                     \
+    macro(f28, "f28", 0, 0)                     \
+    macro(f29, "f29", 0, 0)                     \
+    macro(f30, "f30", 0, 0)                     \
+    macro(f31, "f31", 0, 0)
diff --git a/Source/JavaScriptCore/assembler/RegisterInfo.h b/Source/JavaScriptCore/assembler/RegisterInfo.h
new file mode 100644 (file)
index 0000000..8be60b0
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#pragma once
+
+#include <wtf/Assertions.h>
+
+/* This file serves as the platform independent redirection header for
+ * platform dependent register information. Each architecture has its own header.
+ *
+ * Each header defines a few important macros that are used in a platform independent
+ * way - see for example jit/RegisterSet.cpp.
+ * - FOR_EACH_GP_REGISTER which lists all available general purpose registers.
+ * - FOR_EACH_FP_REGISTER which lists all available floating point registers.
+ * these take themselves a macro that can filter through the available information
+ * spread accross the four macro arguments.
+ * = 1. id: is an identifier used to specify the register (for example, as an enumerator
+ * in an enum);
+ * = 2. name: is a string constant specifying the name of the identifier;
+ * = 3. isReserved: a boolean (usually 0/1) specifying if this is a reserved register;
+ * = 4. isCalleeSaved: a boolean (usually 0/1) specifying if this is a callee saved register;
+ *
+ * - A few other platform dependent macros can be specified to be used in platform
+ *   dependent files (for example assembler X86Assembler.h).
+ */
+
+#if CPU(X86)
+#include "X86Registers.h"
+#elif CPU(X86_64)
+#include "X86_64Registers.h"
+#elif CPU(MIPS)
+#include "MIPSRegisters.h"
+#elif CPU(ARM_THUMB2)
+#include "ARMv7Registers.h"
+#elif CPU(ARM64)
+#include "ARM64Registers.h"
+#else
+    UNREACHABLE_FOR_PLATFORM();
+#endif
index 06cb9e1..5b0c85b 100644 (file)
@@ -30,6 +30,7 @@
 #include "AssemblerBuffer.h"
 #include "AssemblerCommon.h"
 #include "JITCompilationEffort.h"
+#include "RegisterInfo.h"
 #include <limits.h>
 #include <stdint.h>
 #include <wtf/Assertions.h>
@@ -39,7 +40,7 @@ namespace JSC {
 
 inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
 
-namespace X86Registers {
+namespace RegisterNames {
 
 #if COMPILER(MSVC)
 #define JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE
@@ -47,56 +48,25 @@ namespace X86Registers {
 #define JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE : int8_t
 #endif
 
+#define REGISTER_ID(id, name, res, cs) id,
+
 typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
-    eax,
-    ecx,
-    edx,
-    ebx,
-    esp,
-    ebp,
-    esi,
-    edi,
-#if CPU(X86_64)
-    r8,
-    r9,
-    r10,
-    r11,
-    r12,
-    r13,
-    r14,
-    r15,
-#endif
+    FOR_EACH_GP_REGISTER(REGISTER_ID)
     InvalidGPRReg = -1,
 } RegisterID;
 
 typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
-    eip,
-    eflags
+    FOR_EACH_SP_REGISTER(REGISTER_ID)                                                     
 } SPRegisterID;
 
 typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
-    xmm0,
-    xmm1,
-    xmm2,
-    xmm3,
-    xmm4,
-    xmm5,
-    xmm6,
-    xmm7,
-#if CPU(X86_64)
-    xmm8,
-    xmm9,
-    xmm10,
-    xmm11,
-    xmm12,
-    xmm13,
-    xmm14,
-    xmm15,
-#endif
+    FOR_EACH_FP_REGISTER(REGISTER_ID)
     InvalidFPRReg = -1,
 } XMMRegisterID;
 
-} // namespace X86Register
+#undef REGISTER_ID
+
+} // namespace X86Registers
 
 class X86Assembler {
 public:
@@ -137,15 +107,9 @@ public:
     {
         ASSERT(id >= firstRegister() && id <= lastRegister());
         static const char* const nameForRegister[numberOfRegisters()] = {
-#if CPU(X86_64)
-            "rax", "rcx", "rdx", "rbx",
-            "rsp", "rbp", "rsi", "rdi",
-            "r8", "r9", "r10", "r11",
-            "r12", "r13", "r14", "r15"
-#else
-            "eax", "ecx", "edx", "ebx",
-            "esp", "ebp", "esi", "edi",
-#endif
+#define REGISTER_NAME(id, name, res, cs) name,
+        FOR_EACH_GP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
@@ -154,11 +118,9 @@ public:
     {
         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
         static const char* const nameForRegister[numberOfSPRegisters()] = {
-#if CPU(X86_64)
-            "rip", "rflags"
-#else
-            "eip", "eflags"
-#endif
+#define REGISTER_NAME(id, name, res, cs) name,
+        FOR_EACH_SP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[id];
     }
@@ -167,12 +129,9 @@ public:
     {
         ASSERT(reg >= firstFPRegister() && reg <= lastFPRegister());
         static const char* const nameForRegister[numberOfFPRegisters()] = {
-            "xmm0", "xmm1", "xmm2", "xmm3",
-            "xmm4", "xmm5", "xmm6", "xmm7",
-#if CPU(X86_64)
-            "xmm8", "xmm9", "xmm10", "xmm11",
-            "xmm12", "xmm13", "xmm14", "xmm15"
-#endif
+#define REGISTER_NAME(id, name, res, cs) name,
+        FOR_EACH_FP_REGISTER(REGISTER_NAME)
+#undef REGISTER_NAME
         };
         return nameForRegister[reg];
     }
diff --git a/Source/JavaScriptCore/assembler/X86Registers.h b/Source/JavaScriptCore/assembler/X86Registers.h
new file mode 100644 (file)
index 0000000..593a13c
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+#pragma once
+
+#include <wtf/Platform.h>
+
+#define RegisterNames X86Registers
+
+#define FOR_EACH_REGISTER(macro)                \
+    FOR_EACH_GP_REGISTER(macro)                 \
+    FOR_EACH_FP_REGISTER(macro)
+
+#if !OS(WINDOWS)
+
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(eax, "rax", 0, 0)                     \
+    macro(ecx, "rcx", 0, 0)                     \
+    macro(edx, "rdx", 0, 0)                     \
+    macro(ebx, "rbx", 0, 1)                     \
+    macro(esp, "rsp", 0, 0)                     \
+    macro(ebp, "rbp", 0, 1)                     \
+    macro(esi, "rsi", 0, 0)                     \
+    macro(edi, "rdi", 0, 0)
+
+#else // OS(WINDOWS)
+
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(eax, "rax", 0, 0)                     \
+    macro(ecx, "rcx", 0, 0)                     \
+    macro(edx, "rdx", 0, 0)                     \
+    macro(ebx, "rbx", 0, 1)                     \
+    macro(esp, "rsp", 0, 0)                     \
+    macro(ebp, "rbp", 0, 1)                     \
+    macro(esi, "rsi", 0, 1)                     \
+    macro(edi, "rdi", 0, 1)
+
+#endif // !OS(WINDOWS)
+
+#define FOR_EACH_FP_REGISTER(macro)             \
+    macro(xmm0, "xmm0", 0, 0)                   \
+    macro(xmm1, "xmm1", 0, 0)                   \
+    macro(xmm2, "xmm2", 0, 0)                   \
+    macro(xmm3, "xmm3", 0, 0)                   \
+    macro(xmm4, "xmm4", 0, 0)                   \
+    macro(xmm5, "xmm5", 0, 0)                   \
+    macro(xmm6, "xmm6", 0, 0)                   \
+    macro(xmm7, "xmm7", 0, 0)
+
+#define FOR_EACH_SP_REGISTER(macro)             \
+    macro(eip,    "eip",    0, 0)               \
+    macro(eflags, "eflags", 0, 0)
+
diff --git a/Source/JavaScriptCore/assembler/X86_64Registers.h b/Source/JavaScriptCore/assembler/X86_64Registers.h
new file mode 100644 (file)
index 0000000..884bd94
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2019 Metrological Group B.V.
+ * Copyright (C) 2019 Igalia S.L.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#pragma once
+
+#include <wtf/Compiler.h>
+#include <wtf/Platform.h>
+
+#define RegisterNames X86Registers
+
+#if !OS(WINDOWS)
+
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(eax, "rax", 0, 0)                     \
+    macro(ecx, "rcx", 0, 0)                     \
+    macro(edx, "rdx", 0, 0)                     \
+    macro(ebx, "rbx", 0, 1)                     \
+    macro(esp, "rsp", 0, 0)                     \
+    macro(ebp, "rbp", 0, 1)                     \
+    macro(esi, "rsi", 0, 0)                     \
+    macro(edi, "rdi", 0, 0)                     \
+    macro(r8,  "r8",  0, 0)                     \
+    macro(r9,  "r9",  0, 0)                     \
+    macro(r10, "r10", 0, 0)                     \
+    macro(r11, "r11", 0, 0)                     \
+    macro(r12, "r12", 0, 1)                     \
+    macro(r13, "r13", 0, 1)                     \
+    macro(r14, "r14", 0, 1)                     \
+    macro(r15, "r15", 0, 1)
+
+#else // OS(WINDOWS)
+
+#define FOR_EACH_GP_REGISTER(macro)             \
+    macro(eax, "rax", 0, 0)                     \
+    macro(ecx, "rcx", 0, 0)                     \
+    macro(edx, "rdx", 0, 0)                     \
+    macro(ebx, "rbx", 0, 1)                     \
+    macro(esp, "rsp", 0, 0)                     \
+    macro(ebp, "rbp", 0, 1)                     \
+    macro(esi, "rsi", 0, 1)                     \
+    macro(edi, "rdi", 0, 1)                     \
+    macro(r8,  "r8",  0, 0)                     \
+    macro(r9,  "r9",  0, 0)                     \
+    macro(r10, "r10", 0, 0)                     \
+    macro(r11, "r11", 0, 0)                     \
+    macro(r12, "r12", 0, 1)                     \
+    macro(r13, "r13", 0, 1)                     \
+    macro(r14, "r14", 0, 1)                     \
+    macro(r15, "r15", 0, 1)
+
+#endif // !OS(WINDOWS)
+
+#define FOR_EACH_FP_REGISTER(macro)             \
+    macro(xmm0,  "xmm0",  0, 0)                  \
+    macro(xmm1,  "xmm1",  0, 0)                  \
+    macro(xmm2,  "xmm2",  0, 0)                  \
+    macro(xmm3,  "xmm3",  0, 0)                  \
+    macro(xmm4,  "xmm4",  0, 0)                  \
+    macro(xmm5,  "xmm5",  0, 0)                  \
+    macro(xmm6,  "xmm6",  0, 0)                  \
+    macro(xmm7,  "xmm7",  0, 0)                  \
+    macro(xmm8,  "xmm8",  0, 0)                  \
+    macro(xmm9,  "xmm9",  0, 0)                  \
+    macro(xmm10, "xmm10", 0, 0)                  \
+    macro(xmm11, "xmm11", 0, 0)                  \
+    macro(xmm12, "xmm12", 0, 0)                  \
+    macro(xmm13, "xmm13", 0, 0)                  \
+    macro(xmm14, "xmm14", 0, 0)                  \
+    macro(xmm15, "xmm15", 0, 0)
+
+#define FOR_EACH_SP_REGISTER(macro)             \
+    macro(eip,    "eip",    0, 0)               \
+    macro(eflags, "eflags", 0, 0)
index 6bcf676..a3f8755 100644 (file)
@@ -33,7 +33,7 @@ namespace JSC {
 
 enum NoResultTag { NoResult };
 
-// We use the same conventions in the basline JIT as in the LLint. If you
+// We use the same conventions in the baseline JIT as in the LLint. If you
 // change mappings in the GPRInfo, you should change them in the offlineasm
 // compiler adequately. The register naming conventions are described at the
 // top of the LowLevelInterpreter.asm file.
index ed294cb..136560c 100644 (file)
@@ -32,6 +32,7 @@
 #include "JSCInlines.h"
 #include "MacroAssembler.h"
 #include "RegisterAtOffsetList.h"
+#include "assembler/RegisterInfo.h"
 #include <wtf/CommaPrinter.h>
 
 namespace JSC {
@@ -45,17 +46,16 @@ RegisterSet RegisterSet::stackRegisters()
 
 RegisterSet RegisterSet::reservedHardwareRegisters()
 {
-#if CPU(ARM64)
-#if PLATFORM(IOS_FAMILY)
-    return RegisterSet(ARM64Registers::x18, ARM64Registers::lr);
-#else
-    return RegisterSet(ARM64Registers::lr);
-#endif // PLATFORM(IOS_FAMILY)
-#elif CPU(ARM_THUMB2)
-    return RegisterSet(ARMRegisters::lr, ARMRegisters::pc);
-#else
-    return { };
-#endif
+    RegisterSet result;
+
+#define SET_IF_RESERVED(id, name, isReserved, isCalleeSaved)    \
+    if (isReserved)                                             \
+        result.set(RegisterNames::id);
+    FOR_EACH_GP_REGISTER(SET_IF_RESERVED)
+    FOR_EACH_FP_REGISTER(SET_IF_RESERVED)
+#undef SET_IF_RESERVED
+
+    return result;
 }
 
 RegisterSet RegisterSet::runtimeTagRegisters()
@@ -111,53 +111,14 @@ RegisterSet RegisterSet::macroScratchRegisters()
 RegisterSet RegisterSet::calleeSaveRegisters()
 {
     RegisterSet result;
-#if CPU(X86)
-    result.set(X86Registers::ebx);
-    result.set(X86Registers::ebp);
-    result.set(X86Registers::edi);
-    result.set(X86Registers::esi);
-#elif CPU(X86_64)
-    result.set(X86Registers::ebx);
-    result.set(X86Registers::ebp);
-#if OS(WINDOWS)
-    result.set(X86Registers::edi);
-    result.set(X86Registers::esi);
-#endif
-    result.set(X86Registers::r12);
-    result.set(X86Registers::r13);
-    result.set(X86Registers::r14);
-    result.set(X86Registers::r15);
-#elif CPU(ARM_THUMB2)
-    result.set(ARMRegisters::r4);
-    result.set(ARMRegisters::r5);
-    result.set(ARMRegisters::r6);
-    result.set(ARMRegisters::r8);
-#if !PLATFORM(IOS_FAMILY)
-    result.set(ARMRegisters::r9);
-#endif
-    result.set(ARMRegisters::r10);
-    result.set(ARMRegisters::r11);
-#elif CPU(ARM64)
-    // We don't include LR in the set of callee-save registers even though it technically belongs
-    // there. This is because we use this set to describe the set of registers that need to be saved
-    // beyond what you would save by the platform-agnostic "preserve return address" and "restore
-    // return address" operations in CCallHelpers.
-    for (
-        ARM64Registers::RegisterID reg = ARM64Registers::x19;
-        reg <= ARM64Registers::x28;
-        reg = static_cast<ARM64Registers::RegisterID>(reg + 1))
-        result.set(reg);
-    result.set(ARM64Registers::fp);
-    for (
-        ARM64Registers::FPRegisterID reg = ARM64Registers::q8;
-        reg <= ARM64Registers::q15;
-        reg = static_cast<ARM64Registers::FPRegisterID>(reg + 1))
-        result.set(reg);
-#elif CPU(MIPS)
-    result.set(MIPSRegisters::s0);
-#else
-    UNREACHABLE_FOR_PLATFORM();
-#endif
+
+#define SET_IF_CALLEESAVED(id, name, isReserved, isCalleeSaved)        \
+    if (isCalleeSaved)                                                 \
+        result.set(RegisterNames::id);
+    FOR_EACH_GP_REGISTER(SET_IF_CALLEESAVED)
+    FOR_EACH_FP_REGISTER(SET_IF_CALLEESAVED)
+#undef SET_IF_CALLEESAVED
+        
     return result;
 }