[JSC] Drop ARM_TRADITIONAL support in LLInt, baseline JIT, and DFG
authoryusukesuzuki@slowstart.org <yusukesuzuki@slowstart.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Thu, 22 Nov 2018 05:47:05 +0000 (05:47 +0000)
committeryusukesuzuki@slowstart.org <yusukesuzuki@slowstart.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Thu, 22 Nov 2018 05:47:05 +0000 (05:47 +0000)
https://bugs.webkit.org/show_bug.cgi?id=191675

Reviewed by Mark Lam.

Source/JavaScriptCore:

We no longer maintain ARM_TRADITIONAL LLInt and JIT in JSC. This architecture will use
CLoop instead. This patch removes ARM_TRADITIONAL support in LLInt and JIT.

Discussed in https://lists.webkit.org/pipermail/webkit-dev/2018-October/030220.html.

* CMakeLists.txt:
* JavaScriptCore.xcodeproj/project.pbxproj:
* Sources.txt:
* assembler/ARMAssembler.cpp: Removed.
* assembler/ARMAssembler.h: Removed.
* assembler/LinkBuffer.cpp:
(JSC::LinkBuffer::linkCode):
(JSC::LinkBuffer::dumpCode):
* assembler/MacroAssembler.h:
(JSC::MacroAssembler::patchableBranch32):
* assembler/MacroAssemblerARM.cpp: Removed.
* assembler/MacroAssemblerARM.h: Removed.
* assembler/PerfLog.cpp:
* assembler/PerfLog.h:
* assembler/ProbeContext.h:
(JSC::Probe::CPUState::pc):
(JSC::Probe::CPUState::fp):
(JSC::Probe::CPUState::sp):
* assembler/testmasm.cpp:
(JSC::isPC):
(JSC::testProbeModifiesStackPointer):
(JSC::testProbeModifiesStackValues):
* bytecode/InlineAccess.h:
(JSC::InlineAccess::sizeForPropertyAccess):
(JSC::InlineAccess::sizeForPropertyReplace):
(JSC::InlineAccess::sizeForLengthAccess):
* dfg/DFGSpeculativeJIT.h:
* disassembler/CapstoneDisassembler.cpp:
(JSC::tryToDisassemble):
* jit/AssemblyHelpers.cpp:
(JSC::AssemblyHelpers::debugCall):
* jit/AssemblyHelpers.h:
* jit/CCallHelpers.h:
(JSC::CCallHelpers::setupArgumentsImpl):
(JSC::CCallHelpers::prepareForTailCallSlow):
* jit/CallFrameShuffler.cpp:
(JSC::CallFrameShuffler::prepareForTailCall):
* jit/HostCallReturnValue.cpp:
* jit/JITMathIC.h:
(JSC::isProfileEmpty):
* jit/RegisterSet.cpp:
(JSC::RegisterSet::reservedHardwareRegisters):
(JSC::RegisterSet::calleeSaveRegisters):
(JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
(JSC::RegisterSet::dfgCalleeSaveRegisters):
* jit/Repatch.cpp:
(JSC::forceICFailure):
* jit/ThunkGenerators.cpp:
(JSC::nativeForGenerator):
* llint/LLIntOfflineAsmConfig.h:
* llint/LowLevelInterpreter.asm:
* llint/LowLevelInterpreter32_64.asm:
* offlineasm/arm.rb:
* offlineasm/backends.rb:
* yarr/YarrJIT.cpp:
(JSC::Yarr::YarrGenerator::generateEnter):
(JSC::Yarr::YarrGenerator::generateReturn):

Source/WTF:

* wtf/InlineASM.h:
* wtf/Platform.h:

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@238439 268f45cc-cd09-0410-ab3c-d52691b4dbfc

35 files changed:
Source/JavaScriptCore/CMakeLists.txt
Source/JavaScriptCore/ChangeLog
Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj
Source/JavaScriptCore/Sources.txt
Source/JavaScriptCore/assembler/ARMAssembler.cpp [deleted file]
Source/JavaScriptCore/assembler/ARMAssembler.h [deleted file]
Source/JavaScriptCore/assembler/LinkBuffer.cpp
Source/JavaScriptCore/assembler/MacroAssembler.h
Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp [deleted file]
Source/JavaScriptCore/assembler/MacroAssemblerARM.h [deleted file]
Source/JavaScriptCore/assembler/PerfLog.cpp
Source/JavaScriptCore/assembler/PerfLog.h
Source/JavaScriptCore/assembler/ProbeContext.h
Source/JavaScriptCore/assembler/testmasm.cpp
Source/JavaScriptCore/bytecode/InlineAccess.h
Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h
Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp
Source/JavaScriptCore/jit/AssemblyHelpers.cpp
Source/JavaScriptCore/jit/AssemblyHelpers.h
Source/JavaScriptCore/jit/CCallHelpers.h
Source/JavaScriptCore/jit/CallFrameShuffler.cpp
Source/JavaScriptCore/jit/HostCallReturnValue.cpp
Source/JavaScriptCore/jit/JITMathIC.h
Source/JavaScriptCore/jit/RegisterSet.cpp
Source/JavaScriptCore/jit/Repatch.cpp
Source/JavaScriptCore/jit/ThunkGenerators.cpp
Source/JavaScriptCore/llint/LLIntOfflineAsmConfig.h
Source/JavaScriptCore/llint/LowLevelInterpreter.asm
Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm
Source/JavaScriptCore/offlineasm/arm.rb
Source/JavaScriptCore/offlineasm/backends.rb
Source/JavaScriptCore/yarr/YarrJIT.cpp
Source/WTF/ChangeLog
Source/WTF/wtf/InlineASM.h
Source/WTF/wtf/Platform.h

index ab87254..79cab0b 100644 (file)
@@ -240,8 +240,6 @@ else ()
         set(OFFLINE_ASM_BACKEND "ARM64")
     elseif (ARM_THUMB2_DETECTED)
         set(OFFLINE_ASM_BACKEND "ARMv7")
-    elseif (ARM_TRADITIONAL_DETECTED)
-        set(OFFLINE_ASM_BACKEND "ARMv7_TRADITIONAL")
     elseif (WTF_CPU_MIPS)
         set(OFFLINE_ASM_BACKEND "MIPS")
     endif ()
@@ -424,7 +422,6 @@ set(JavaScriptCore_PRIVATE_FRAMEWORK_HEADERS
     API/OpaqueJSString.h
 
     assembler/ARM64Assembler.h
-    assembler/ARMAssembler.h
     assembler/ARMv7Assembler.h
     assembler/AbortReason.h
     assembler/AbstractMacroAssembler.h
@@ -436,7 +433,6 @@ set(JavaScriptCore_PRIVATE_FRAMEWORK_HEADERS
     assembler/LinkBuffer.h
     assembler/MIPSAssembler.h
     assembler/MacroAssembler.h
-    assembler/MacroAssemblerARM.h
     assembler/MacroAssemblerARM64.h
     assembler/MacroAssemblerARMv7.h
     assembler/MacroAssemblerCodeRef.h
index ffb9fc3..0dc88d8 100644 (file)
@@ -1,3 +1,73 @@
+2018-11-21  Yusuke Suzuki  <yusukesuzuki@slowstart.org>
+
+        [JSC] Drop ARM_TRADITIONAL support in LLInt, baseline JIT, and DFG
+        https://bugs.webkit.org/show_bug.cgi?id=191675
+
+        Reviewed by Mark Lam.
+
+        We no longer maintain ARM_TRADITIONAL LLInt and JIT in JSC. This architecture will use
+        CLoop instead. This patch removes ARM_TRADITIONAL support in LLInt and JIT.
+
+        Discussed in https://lists.webkit.org/pipermail/webkit-dev/2018-October/030220.html.
+
+        * CMakeLists.txt:
+        * JavaScriptCore.xcodeproj/project.pbxproj:
+        * Sources.txt:
+        * assembler/ARMAssembler.cpp: Removed.
+        * assembler/ARMAssembler.h: Removed.
+        * assembler/LinkBuffer.cpp:
+        (JSC::LinkBuffer::linkCode):
+        (JSC::LinkBuffer::dumpCode):
+        * assembler/MacroAssembler.h:
+        (JSC::MacroAssembler::patchableBranch32):
+        * assembler/MacroAssemblerARM.cpp: Removed.
+        * assembler/MacroAssemblerARM.h: Removed.
+        * assembler/PerfLog.cpp:
+        * assembler/PerfLog.h:
+        * assembler/ProbeContext.h:
+        (JSC::Probe::CPUState::pc):
+        (JSC::Probe::CPUState::fp):
+        (JSC::Probe::CPUState::sp):
+        * assembler/testmasm.cpp:
+        (JSC::isPC):
+        (JSC::testProbeModifiesStackPointer):
+        (JSC::testProbeModifiesStackValues):
+        * bytecode/InlineAccess.h:
+        (JSC::InlineAccess::sizeForPropertyAccess):
+        (JSC::InlineAccess::sizeForPropertyReplace):
+        (JSC::InlineAccess::sizeForLengthAccess):
+        * dfg/DFGSpeculativeJIT.h:
+        * disassembler/CapstoneDisassembler.cpp:
+        (JSC::tryToDisassemble):
+        * jit/AssemblyHelpers.cpp:
+        (JSC::AssemblyHelpers::debugCall):
+        * jit/AssemblyHelpers.h:
+        * jit/CCallHelpers.h:
+        (JSC::CCallHelpers::setupArgumentsImpl):
+        (JSC::CCallHelpers::prepareForTailCallSlow):
+        * jit/CallFrameShuffler.cpp:
+        (JSC::CallFrameShuffler::prepareForTailCall):
+        * jit/HostCallReturnValue.cpp:
+        * jit/JITMathIC.h:
+        (JSC::isProfileEmpty):
+        * jit/RegisterSet.cpp:
+        (JSC::RegisterSet::reservedHardwareRegisters):
+        (JSC::RegisterSet::calleeSaveRegisters):
+        (JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
+        (JSC::RegisterSet::dfgCalleeSaveRegisters):
+        * jit/Repatch.cpp:
+        (JSC::forceICFailure):
+        * jit/ThunkGenerators.cpp:
+        (JSC::nativeForGenerator):
+        * llint/LLIntOfflineAsmConfig.h:
+        * llint/LowLevelInterpreter.asm:
+        * llint/LowLevelInterpreter32_64.asm:
+        * offlineasm/arm.rb:
+        * offlineasm/backends.rb:
+        * yarr/YarrJIT.cpp:
+        (JSC::Yarr::YarrGenerator::generateEnter):
+        (JSC::Yarr::YarrGenerator::generateReturn):
+
 2018-11-21  Saam barati  <sbarati@apple.com>
 
         DFGSpeculativeJIT should not &= exitOK with mayExit(node)
index ee45711..c277ebf 100644 (file)
                86CC85A10EE79A4700288682 /* JITInlines.h in Headers */ = {isa = PBXBuildFile; fileRef = 86CC85A00EE79A4700288682 /* JITInlines.h */; };
                86CCEFDE0F413F8900FD7F9E /* JITCode.h in Headers */ = {isa = PBXBuildFile; fileRef = 86CCEFDD0F413F8900FD7F9E /* JITCode.h */; settings = {ATTRIBUTES = (Private, ); }; };
                86D2221A167EF9440024C804 /* testapi.mm in Sources */ = {isa = PBXBuildFile; fileRef = 86D22219167EF9440024C804 /* testapi.mm */; };
-               86D3B2C410156BDE002865E7 /* ARMAssembler.h in Headers */ = {isa = PBXBuildFile; fileRef = 86D3B2C010156BDE002865E7 /* ARMAssembler.h */; settings = {ATTRIBUTES = (Private, ); }; };
                86D3B2C510156BDE002865E7 /* AssemblerBufferWithConstantPool.h in Headers */ = {isa = PBXBuildFile; fileRef = 86D3B2C110156BDE002865E7 /* AssemblerBufferWithConstantPool.h */; settings = {ATTRIBUTES = (Private, ); }; };
-               86D3B2C610156BDE002865E7 /* MacroAssemblerARM.h in Headers */ = {isa = PBXBuildFile; fileRef = 86D3B2C210156BDE002865E7 /* MacroAssemblerARM.h */; settings = {ATTRIBUTES = (Private, ); }; };
                86D3B3C310159D7F002865E7 /* LinkBuffer.h in Headers */ = {isa = PBXBuildFile; fileRef = 86D3B3C110159D7F002865E7 /* LinkBuffer.h */; settings = {ATTRIBUTES = (Private, ); }; };
                86E116B10FE75AC800B512BC /* CodeLocation.h in Headers */ = {isa = PBXBuildFile; fileRef = 86E116B00FE75AC800B512BC /* CodeLocation.h */; settings = {ATTRIBUTES = (Private, ); }; };
                86E3C612167BABD7006D760A /* JSValue.h in Headers */ = {isa = PBXBuildFile; fileRef = 86E3C606167BAB87006D760A /* JSValue.h */; settings = {ATTRIBUTES = (Public, ); }; };
                86B5826A14D35D5100A9C306 /* TieredMMapArray.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TieredMMapArray.h; sourceTree = "<group>"; };
                86BF642A148DB2B5004DE36A /* Intrinsic.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Intrinsic.h; sourceTree = "<group>"; };
                86C36EE90EE1289D00B3DF59 /* MacroAssembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MacroAssembler.h; sourceTree = "<group>"; };
-               86C568DD11A213EE0007F7F0 /* MacroAssemblerARM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = MacroAssemblerARM.cpp; sourceTree = "<group>"; };
                86C568DE11A213EE0007F7F0 /* MacroAssemblerMIPS.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MacroAssemblerMIPS.h; sourceTree = "<group>"; };
                86C568DF11A213EE0007F7F0 /* MIPSAssembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MIPSAssembler.h; sourceTree = "<group>"; };
                86CC85A00EE79A4700288682 /* JITInlines.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = JITInlines.h; sourceTree = "<group>"; };
                86CC85C30EE7A89400288682 /* JITPropertyAccess.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = JITPropertyAccess.cpp; sourceTree = "<group>"; };
                86CCEFDD0F413F8900FD7F9E /* JITCode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = JITCode.h; sourceTree = "<group>"; };
                86D22219167EF9440024C804 /* testapi.mm */ = {isa = PBXFileReference; explicitFileType = sourcecode.cpp.objcpp; fileEncoding = 4; name = testapi.mm; path = API/tests/testapi.mm; sourceTree = "<group>"; };
-               86D3B2BF10156BDE002865E7 /* ARMAssembler.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = ARMAssembler.cpp; sourceTree = "<group>"; };
-               86D3B2C010156BDE002865E7 /* ARMAssembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = ARMAssembler.h; sourceTree = "<group>"; };
                86D3B2C110156BDE002865E7 /* AssemblerBufferWithConstantPool.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = AssemblerBufferWithConstantPool.h; sourceTree = "<group>"; };
-               86D3B2C210156BDE002865E7 /* MacroAssemblerARM.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MacroAssemblerARM.h; sourceTree = "<group>"; };
                86D3B3C110159D7F002865E7 /* LinkBuffer.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = LinkBuffer.h; sourceTree = "<group>"; };
                86E116B00FE75AC800B512BC /* CodeLocation.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = CodeLocation.h; sourceTree = "<group>"; };
                86E3C606167BAB87006D760A /* JSValue.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = JSValue.h; sourceTree = "<group>"; };
                                0F3730901C0CD70C00052BFA /* AllowMacroScratchRegisterUsage.h */,
                                AD412B351E7B57C0008AF157 /* AllowMacroScratchRegisterUsageIf.h */,
                                8640923B156EED3B00566CB2 /* ARM64Assembler.h */,
-                               86D3B2BF10156BDE002865E7 /* ARMAssembler.cpp */,
-                               86D3B2C010156BDE002865E7 /* ARMAssembler.h */,
                                86ADD1430FDDEA980006EEC2 /* ARMv7Assembler.h */,
                                9688CB130ED12B4E001D649F /* AssemblerBuffer.h */,
                                86D3B2C110156BDE002865E7 /* AssemblerBufferWithConstantPool.h */,
                                86D3B3C110159D7F002865E7 /* LinkBuffer.h */,
                                0FEB3ECE16237F6700AB67AD /* MacroAssembler.cpp */,
                                86C36EE90EE1289D00B3DF59 /* MacroAssembler.h */,
-                               86C568DD11A213EE0007F7F0 /* MacroAssemblerARM.cpp */,
-                               86D3B2C210156BDE002865E7 /* MacroAssemblerARM.h */,
                                FEB137561BB11EEE00CD5100 /* MacroAssemblerARM64.cpp */,
                                8640923C156EED3B00566CB2 /* MacroAssemblerARM64.h */,
                                A729009B17976C6000317298 /* MacroAssemblerARMv7.cpp */,
                                79A228361D35D71F00D8E067 /* ArithProfile.h in Headers */,
                                0F6B1CB91861244C00845D97 /* ArityCheckMode.h in Headers */,
                                A1A009C11831A26E00CF8711 /* ARM64Assembler.h in Headers */,
-                               86D3B2C410156BDE002865E7 /* ARMAssembler.h in Headers */,
                                86ADD1450FDDEA980006EEC2 /* ARMv7Assembler.h in Headers */,
                                0F8335B81639C1EA001443B5 /* ArrayAllocationProfile.h in Headers */,
                                A7A8AF3517ADB5F3005AB174 /* ArrayBuffer.h in Headers */,
                                981ED82328234D91BAECCADE /* MachineContext.h in Headers */,
                                14B723B812D7DA6F003BD5ED /* MachineStackMarker.h in Headers */,
                                86C36EEA0EE1289D00B3DF59 /* MacroAssembler.h in Headers */,
-                               86D3B2C610156BDE002865E7 /* MacroAssemblerARM.h in Headers */,
                                A1A009C01831A22D00CF8711 /* MacroAssemblerARM64.h in Headers */,
                                86ADD1460FDDEA980006EEC2 /* MacroAssemblerARMv7.h in Headers */,
                                863B23E00FC6118900703AA4 /* MacroAssemblerCodeRef.h in Headers */,
index 1ad99f0..cba4c4b 100644 (file)
@@ -41,11 +41,9 @@ API/JSWeakPrivate.cpp
 API/JSWeakValue.cpp
 API/OpaqueJSString.cpp
 
-assembler/ARMAssembler.cpp
 assembler/AbstractMacroAssembler.cpp
 assembler/LinkBuffer.cpp
 assembler/MacroAssembler.cpp
-assembler/MacroAssemblerARM.cpp
 assembler/MacroAssemblerARM64.cpp
 assembler/MacroAssemblerARMv7.cpp
 assembler/MacroAssemblerCodeRef.cpp
diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.cpp b/Source/JavaScriptCore/assembler/ARMAssembler.cpp
deleted file mode 100644 (file)
index 552f37f..0000000
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
- * Copyright (C) 2009 University of Szeged
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY UNIVERSITY OF SZEGED ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL UNIVERSITY OF SZEGED OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "config.h"
-
-#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
-
-#include "ARMAssembler.h"
-
-namespace JSC {
-
-// Patching helpers
-
-void ARMAssembler::patchConstantPoolLoad(void* loadAddr, void* constPoolAddr)
-{
-    ARMWord *ldr = reinterpret_cast<ARMWord*>(loadAddr);
-    ARMWord diff = reinterpret_cast<ARMWord*>(constPoolAddr) - ldr;
-    ARMWord index = (*ldr & 0xfff) >> 1;
-
-    ASSERT(diff >= 1);
-    if (diff >= 2 || index > 0) {
-        diff = (diff + index - 2) * sizeof(ARMWord);
-        ASSERT(diff <= 0xfff);
-        *ldr = (*ldr & ~0xfff) | diff;
-    } else
-        *ldr = (*ldr & ~(0xfff | ARMAssembler::DataTransferUp)) | sizeof(ARMWord);
-}
-
-// Handle immediates
-
-ARMWord ARMAssembler::getOp2(ARMWord imm)
-{
-    int rol;
-
-    if (imm <= 0xff)
-        return Op2Immediate | imm;
-
-    if ((imm & 0xff000000) == 0) {
-        imm <<= 8;
-        rol = 8;
-    }
-    else {
-        imm = (imm << 24) | (imm >> 8);
-        rol = 0;
-    }
-
-    if ((imm & 0xff000000) == 0) {
-        imm <<= 8;
-        rol += 4;
-    }
-
-    if ((imm & 0xf0000000) == 0) {
-        imm <<= 4;
-        rol += 2;
-    }
-
-    if ((imm & 0xc0000000) == 0) {
-        imm <<= 2;
-        rol += 1;
-    }
-
-    if ((imm & 0x00ffffff) == 0)
-        return Op2Immediate | (imm >> 24) | (rol << 8);
-
-    return InvalidImmediate;
-}
-
-int ARMAssembler::genInt(int reg, ARMWord imm, bool positive)
-{
-    // Step1: Search a non-immediate part
-    ARMWord mask;
-    ARMWord imm1;
-    ARMWord imm2;
-    int rol;
-
-    mask = 0xff000000;
-    rol = 8;
-    while(1) {
-        if ((imm & mask) == 0) {
-            imm = (imm << rol) | (imm >> (32 - rol));
-            rol = 4 + (rol >> 1);
-            break;
-        }
-        rol += 2;
-        mask >>= 2;
-        if (mask & 0x3) {
-            // rol 8
-            imm = (imm << 8) | (imm >> 24);
-            mask = 0xff00;
-            rol = 24;
-            while (1) {
-                if ((imm & mask) == 0) {
-                    imm = (imm << rol) | (imm >> (32 - rol));
-                    rol = (rol >> 1) - 8;
-                    break;
-                }
-                rol += 2;
-                mask >>= 2;
-                if (mask & 0x3)
-                    return 0;
-            }
-            break;
-        }
-    }
-
-    ASSERT((imm & 0xff) == 0);
-
-    if ((imm & 0xff000000) == 0) {
-        imm1 = Op2Immediate | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8);
-        imm2 = Op2Immediate | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8);
-    } else if (imm & 0xc0000000) {
-        imm1 = Op2Immediate | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
-        imm <<= 8;
-        rol += 4;
-
-        if ((imm & 0xff000000) == 0) {
-            imm <<= 8;
-            rol += 4;
-        }
-
-        if ((imm & 0xf0000000) == 0) {
-            imm <<= 4;
-            rol += 2;
-        }
-
-        if ((imm & 0xc0000000) == 0) {
-            imm <<= 2;
-            rol += 1;
-        }
-
-        if ((imm & 0x00ffffff) == 0)
-            imm2 = Op2Immediate | (imm >> 24) | ((rol & 0xf) << 8);
-        else
-            return 0;
-    } else {
-        if ((imm & 0xf0000000) == 0) {
-            imm <<= 4;
-            rol += 2;
-        }
-
-        if ((imm & 0xc0000000) == 0) {
-            imm <<= 2;
-            rol += 1;
-        }
-
-        imm1 = Op2Immediate | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
-        imm <<= 8;
-        rol += 4;
-
-        if ((imm & 0xf0000000) == 0) {
-            imm <<= 4;
-            rol += 2;
-        }
-
-        if ((imm & 0xc0000000) == 0) {
-            imm <<= 2;
-            rol += 1;
-        }
-
-        if ((imm & 0x00ffffff) == 0)
-            imm2 = Op2Immediate | (imm >> 24) | ((rol & 0xf) << 8);
-        else
-            return 0;
-    }
-
-    if (positive) {
-        mov(reg, imm1);
-        orr(reg, reg, imm2);
-    } else {
-        mvn(reg, imm1);
-        bic(reg, reg, imm2);
-    }
-
-    return 1;
-}
-
-ARMWord ARMAssembler::getImm(ARMWord imm, int tmpReg, bool invert)
-{
-    ARMWord tmp;
-
-    // Do it by 1 instruction
-    tmp = getOp2(imm);
-    if (tmp != InvalidImmediate)
-        return tmp;
-
-    tmp = getOp2(~imm);
-    if (tmp != InvalidImmediate) {
-        if (invert)
-            return tmp | Op2InvertedImmediate;
-        mvn(tmpReg, tmp);
-        return tmpReg;
-    }
-
-    return encodeComplexImm(imm, tmpReg);
-}
-
-void ARMAssembler::moveImm(ARMWord imm, int dest)
-{
-    ARMWord tmp;
-
-    // Do it by 1 instruction
-    tmp = getOp2(imm);
-    if (tmp != InvalidImmediate) {
-        mov(dest, tmp);
-        return;
-    }
-
-    tmp = getOp2(~imm);
-    if (tmp != InvalidImmediate) {
-        mvn(dest, tmp);
-        return;
-    }
-
-    encodeComplexImm(imm, dest);
-}
-
-ARMWord ARMAssembler::encodeComplexImm(ARMWord imm, int dest)
-{
-#if WTF_ARM_ARCH_AT_LEAST(7)
-    ARMWord tmp = getImm16Op2(imm);
-    if (tmp != InvalidImmediate) {
-        movw(dest, tmp);
-        return dest;
-    }
-    movw(dest, getImm16Op2(imm & 0xffff));
-    movt(dest, getImm16Op2(imm >> 16));
-    return dest;
-#else
-    // Do it by 2 instruction
-    if (genInt(dest, imm, true))
-        return dest;
-    if (genInt(dest, ~imm, false))
-        return dest;
-
-    ldrImmediate(dest, imm);
-    return dest;
-#endif
-}
-
-// Memory load/store helpers
-
-void ARMAssembler::dataTransfer32(DataTransferTypeA transferType, RegisterID srcDst, RegisterID base, int32_t offset)
-{
-    if (offset >= 0) {
-        if (offset <= 0xfff)
-            dtrUp(transferType, srcDst, base, offset);
-        else if (offset <= 0xfffff) {
-            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
-            dtrUp(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
-        } else {
-            moveImm(offset, ARMRegisters::S0);
-            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-        }
-    } else {
-        if (offset >= -0xfff)
-            dtrDown(transferType, srcDst, base, -offset);
-        else if (offset >= -0xfffff) {
-            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
-            dtrDown(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
-        } else {
-            moveImm(offset, ARMRegisters::S0);
-            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-        }
-    }
-}
-
-void ARMAssembler::baseIndexTransfer32(DataTransferTypeA transferType, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
-{
-    ASSERT(scale >= 0 && scale <= 3);
-    ARMWord op2 = lsl(index, scale);
-
-    if (!offset) {
-        dtrUpRegister(transferType, srcDst, base, op2);
-        return;
-    }
-
-    if (offset <= 0xfffff && offset >= -0xfffff) {
-        add(ARMRegisters::S0, base, op2);
-        dataTransfer32(transferType, srcDst, ARMRegisters::S0, offset);
-        return;
-    }
-
-    moveImm(offset, ARMRegisters::S0);
-    add(ARMRegisters::S0, ARMRegisters::S0, op2);
-    dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-}
-
-void ARMAssembler::dataTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, int32_t offset)
-{
-    if (offset >= 0) {
-        if (offset <= 0xff)
-            halfDtrUp(transferType, srcDst, base, getOp2Half(offset));
-        else if (offset <= 0xffff) {
-            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
-            halfDtrUp(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
-        } else {
-            moveImm(offset, ARMRegisters::S0);
-            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-        }
-    } else {
-        if (offset >= -0xff)
-            halfDtrDown(transferType, srcDst, base, getOp2Half(-offset));
-        else if (offset >= -0xffff) {
-            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
-            halfDtrDown(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
-        } else {
-            moveImm(offset, ARMRegisters::S0);
-            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-        }
-    }
-}
-
-void ARMAssembler::baseIndexTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
-{
-    if (!scale && !offset) {
-        halfDtrUpRegister(transferType, srcDst, base, index);
-        return;
-    }
-
-    ARMWord op2 = lsl(index, scale);
-
-    if (offset <= 0xffff && offset >= -0xffff) {
-        add(ARMRegisters::S0, base, op2);
-        dataTransfer16(transferType, srcDst, ARMRegisters::S0, offset);
-        return;
-    }
-
-    moveImm(offset, ARMRegisters::S0);
-    add(ARMRegisters::S0, ARMRegisters::S0, op2);
-    halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
-}
-
-void ARMAssembler::dataTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, int32_t offset)
-{
-    // VFP cannot directly access memory that is not four-byte-aligned
-    if (!(offset & 0x3)) {
-        if (offset <= 0x3ff && offset >= 0) {
-            doubleDtrUp(transferType, srcDst, base, offset >> 2);
-            return;
-        }
-        if (offset <= 0x3ffff && offset >= 0) {
-            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
-            doubleDtrUp(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
-            return;
-        }
-        offset = -offset;
-
-        if (offset <= 0x3ff && offset >= 0) {
-            doubleDtrDown(transferType, srcDst, base, offset >> 2);
-            return;
-        }
-        if (offset <= 0x3ffff && offset >= 0) {
-            sub(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
-            doubleDtrDown(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
-            return;
-        }
-        offset = -offset;
-    }
-
-    moveImm(offset, ARMRegisters::S0);
-    add(ARMRegisters::S0, ARMRegisters::S0, base);
-    doubleDtrUp(transferType, srcDst, ARMRegisters::S0, 0);
-}
-
-void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
-{
-    add(ARMRegisters::S1, base, lsl(index, scale));
-    dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset);
-}
-
-void ARMAssembler::prepareExecutableCopy(void* to)
-{
-    // 64-bit alignment is required for next constant pool and JIT code as well
-    m_buffer.flushWithoutBarrier(true);
-
-    char* data = reinterpret_cast<char*>(m_buffer.data());
-    ptrdiff_t delta = reinterpret_cast<char*>(to) - data;
-
-    for (Jumps::Iterator iter = m_jumps.begin(); iter != m_jumps.end(); ++iter) {
-        // The last bit is set if the constant must be placed on constant pool.
-        int pos = (iter->m_offset) & (~0x1);
-        ARMWord* ldrAddr = reinterpret_cast_ptr<ARMWord*>(data + pos);
-        ARMWord* addr = getLdrImmAddress(ldrAddr);
-        if (*addr != InvalidBranchTarget) {
-            if (!(iter->m_offset & 1)) {
-                intptr_t difference = reinterpret_cast_ptr<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetchOffset);
-
-                if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
-                    *ldrAddr = B | getConditionalField(*ldrAddr) | (difference & BranchOffsetMask);
-                    continue;
-                }
-            }
-            *addr = reinterpret_cast<ARMWord>(data + delta + *addr);
-        }
-    }
-}
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.h b/Source/JavaScriptCore/assembler/ARMAssembler.h
deleted file mode 100644 (file)
index 50b6dcb..0000000
+++ /dev/null
@@ -1,1259 +0,0 @@
-/*
- * Copyright (C) 2009, 2010 University of Szeged
- * Copyright (C) 2017 Apple Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY UNIVERSITY OF SZEGED ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL UNIVERSITY OF SZEGED OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#pragma once
-
-#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
-
-#include "AssemblerBufferWithConstantPool.h"
-#include "JITCompilationEffort.h"
-#include <wtf/Assertions.h>
-namespace JSC {
-
-    typedef uint32_t ARMWord;
-
-    namespace ARMRegisters {
-
-        typedef enum : int8_t {
-            r0,
-            r1,
-            r2,
-            r3,
-            r4,
-            r5,
-            r6,
-            r7,
-            r8,
-            r9,
-            r10,
-            fp,
-            ip,
-            sp,
-            lr,
-            pc,
-
-            // Pseudonyms for some of the registers.
-            S0 = r6,
-            r11 = fp, // frame pointer
-            r12 = ip, S1 = ip,
-            r13 = sp,
-            r14 = lr,
-            r15 = pc,
-            InvalidGPRReg = -1,
-        } RegisterID;
-
-        typedef enum : int8_t {
-            apsr,
-            fpscr
-        } SPRegisterID;
-
-        typedef enum : int8_t {
-            d0,
-            d1,
-            d2,
-            d3,
-            d4,
-            d5,
-            d6,
-            d7,
-            d8,
-            d9,
-            d10,
-            d11,
-            d12,
-            d13,
-            d14,
-            d15,
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-            d16,
-            d17,
-            d18,
-            d19,
-            d20,
-            d21,
-            d22,
-            d23,
-            d24,
-            d25,
-            d26,
-            d27,
-            d28,
-            d29,
-            d30,
-            d31,
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-            InvalidFPRReg = -1,
-        } FPRegisterID;
-
-    } // namespace ARMRegisters
-
-    class ARMAssembler {
-    public:
-        typedef ARMRegisters::RegisterID RegisterID;
-        typedef ARMRegisters::SPRegisterID SPRegisterID;
-        typedef ARMRegisters::FPRegisterID FPRegisterID;
-        typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
-        typedef SegmentedVector<AssemblerLabel, 64> Jumps;
-
-        ARMAssembler()
-            : m_indexOfTailOfLastWatchpoint(1)
-        {
-        }
-
-        ARMBuffer& buffer() { return m_buffer; }
-
-        static constexpr RegisterID firstRegister() { return ARMRegisters::r0; }
-        static constexpr RegisterID lastRegister() { return ARMRegisters::r15; }
-        static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
-
-        static constexpr SPRegisterID firstSPRegister() { return ARMRegisters::apsr; }
-        static constexpr SPRegisterID lastSPRegister() { return ARMRegisters::fpscr; }
-        static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
-
-        static constexpr FPRegisterID firstFPRegister() { return ARMRegisters::d0; }
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-        static constexpr FPRegisterID lastFPRegister() { return ARMRegisters::d31; }
-#else
-        static constexpr FPRegisterID lastFPRegister() { return ARMRegisters::d15; }
-#endif
-        static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
-
-        static const char* gprName(RegisterID id)
-        {
-            ASSERT(id >= firstRegister() && id <= lastRegister());
-            static const char* const nameForRegister[numberOfRegisters()] = {
-                "r0", "r1", "r2", "r3",
-                "r4", "r5", "r6", "r7",
-                "r8", "r9", "r10", "fp",
-                "ip", "sp", "lr", "pc"
-            };
-            return nameForRegister[id];
-        }
-
-        static const char* sprName(SPRegisterID id)
-        {
-            ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
-            static const char* const nameForRegister[numberOfSPRegisters()] = {
-                "apsr", "fpscr"
-            };
-            return nameForRegister[id];
-        }
-
-        static const char* fprName(FPRegisterID id)
-        {
-            ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
-            static const char* const nameForRegister[numberOfFPRegisters()] = {
-                "d0", "d1", "d2", "d3",
-                "d4", "d5", "d6", "d7",
-                "d8", "d9", "d10", "d11",
-                "d12", "d13", "d14", "d15",
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-                "d16", "d17", "d18", "d19",
-                "d20", "d21", "d22", "d23",
-                "d24", "d25", "d26", "d27",
-                "d28", "d29", "d30", "d31"
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-            };
-            return nameForRegister[id];
-        }
-
-        // ARM conditional constants
-        typedef enum {
-            EQ = 0x00000000, // Zero / Equal.
-            NE = 0x10000000, // Non-zero / Not equal.
-            CS = 0x20000000, // Unsigned higher or same.
-            CC = 0x30000000, // Unsigned lower.
-            MI = 0x40000000, // Negative.
-            PL = 0x50000000, // Positive or zero.
-            VS = 0x60000000, // Overflowed.
-            VC = 0x70000000, // Not overflowed.
-            HI = 0x80000000, // Unsigned higher.
-            LS = 0x90000000, // Unsigned lower or same.
-            GE = 0xa0000000, // Signed greater than or equal.
-            LT = 0xb0000000, // Signed less than.
-            GT = 0xc0000000, // Signed greater than.
-            LE = 0xd0000000, // Signed less than or equal.
-            AL = 0xe0000000  // Unconditional / Always execute.
-        } Condition;
-
-        // ARM instruction constants
-        enum {
-            AND = (0x0 << 21),
-            EOR = (0x1 << 21),
-            SUB = (0x2 << 21),
-            RSB = (0x3 << 21),
-            ADD = (0x4 << 21),
-            ADC = (0x5 << 21),
-            SBC = (0x6 << 21),
-            RSC = (0x7 << 21),
-            TST = (0x8 << 21),
-            TEQ = (0x9 << 21),
-            CMP = (0xa << 21),
-            CMN = (0xb << 21),
-            ORR = (0xc << 21),
-            MOV = (0xd << 21),
-            BIC = (0xe << 21),
-            MVN = (0xf << 21),
-            MUL = 0x00000090,
-            MULL = 0x00c00090,
-            VMOV_F64 = 0x0eb00b40,
-            VADD_F64 = 0x0e300b00,
-            VDIV_F64 = 0x0e800b00,
-            VSUB_F64 = 0x0e300b40,
-            VMUL_F64 = 0x0e200b00,
-            VCMP_F64 = 0x0eb40b40,
-            VSQRT_F64 = 0x0eb10bc0,
-            VABS_F64 = 0x0eb00bc0,
-            VNEG_F64 = 0x0eb10b40,
-            STMDB = 0x09200000,
-            LDMIA = 0x08b00000,
-            B = 0x0a000000,
-            BL = 0x0b000000,
-            BX = 0x012fff10,
-            VMOV_VFP64 = 0x0c400a10,
-            VMOV_ARM64 = 0x0c500a10,
-            VMOV_VFP32 = 0x0e000a10,
-            VMOV_ARM32 = 0x0e100a10,
-            VCVT_F64_S32 = 0x0eb80bc0,
-            VCVT_S32_F64 = 0x0ebd0bc0,
-            VCVT_U32_F64 = 0x0ebc0bc0,
-            VCVT_F32_F64 = 0x0eb70bc0,
-            VCVT_F64_F32 = 0x0eb70ac0,
-            VMRS_APSR = 0x0ef1fa10,
-            CLZ = 0x016f0f10,
-            BKPT = 0xe1200070,
-            BLX = 0x012fff30,
-#if WTF_ARM_ARCH_AT_LEAST(7)
-            MOVW = 0x03000000,
-            MOVT = 0x03400000,
-#endif
-            NOP = 0xe1a00000,
-            DMB_SY = 0xf57ff05f,
-            DMB_ISHST = 0xf57ff05a,
-#if HAVE(ARM_IDIV_INSTRUCTIONS)
-            SDIV = 0x0710f010,
-            UDIV = 0x0730f010,
-#endif
-        };
-
-        enum {
-            Op2Immediate = (1 << 25),
-            ImmediateForHalfWordTransfer = (1 << 22),
-            Op2InvertedImmediate = (1 << 26),
-            SetConditionalCodes = (1 << 20),
-            Op2IsRegisterArgument = (1 << 25),
-            // Data transfer flags.
-            DataTransferUp = (1 << 23),
-            DataTransferWriteBack = (1 << 21),
-            DataTransferPostUpdate = (1 << 24),
-            DataTransferLoad = (1 << 20),
-            ByteDataTransfer = (1 << 22),
-        };
-
-        enum DataTransferTypeA {
-            LoadUint32 = 0x05000000 | DataTransferLoad,
-            LoadUint8 = 0x05400000 | DataTransferLoad,
-            StoreUint32 = 0x05000000,
-            StoreUint8 = 0x05400000,
-        };
-
-        enum DataTransferTypeB {
-            LoadUint16 = 0x010000b0 | DataTransferLoad,
-            LoadInt16 = 0x010000f0 | DataTransferLoad,
-            LoadInt8 = 0x010000d0 | DataTransferLoad,
-            StoreUint16 = 0x010000b0,
-        };
-
-        enum DataTransferTypeFloat {
-            LoadFloat = 0x0d000a00 | DataTransferLoad,
-            LoadDouble = 0x0d000b00 | DataTransferLoad,
-            StoreFloat = 0x0d000a00,
-            StoreDouble = 0x0d000b00,
-        };
-
-        // Masks of ARM instructions
-        enum {
-            BranchOffsetMask = 0x00ffffff,
-            ConditionalFieldMask = 0xf0000000,
-            DataTransferOffsetMask = 0xfff,
-        };
-
-        enum {
-            MinimumBranchOffsetDistance = -0x00800000,
-            MaximumBranchOffsetDistance = 0x007fffff,
-        };
-
-        enum {
-            padForAlign8  = 0x00,
-            padForAlign16 = 0x0000,
-            padForAlign32 = 0xe12fff7f // 'bkpt 0xffff' instruction.
-        };
-
-        static const ARMWord InvalidImmediate = 0xf0000000;
-        static const ARMWord InvalidBranchTarget = 0xffffffff;
-        static const int DefaultPrefetchOffset = 2;
-
-        static const ARMWord BlxInstructionMask = 0x012fff30;
-        static const ARMWord LdrOrAddInstructionMask = 0x0ff00000;
-        static const ARMWord LdrPcImmediateInstructionMask = 0x0f7f0000;
-
-        static const ARMWord AddImmediateInstruction = 0x02800000;
-        static const ARMWord BlxInstruction = 0x012fff30;
-        static const ARMWord LdrImmediateInstruction = 0x05900000;
-        static const ARMWord LdrPcImmediateInstruction = 0x051f0000;
-
-        // Instruction formating
-
-        void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2)
-        {
-            ASSERT(((op2 & ~Op2Immediate) <= 0xfff) || (((op2 & ~ImmediateForHalfWordTransfer) <= 0xfff)));
-            m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
-        }
-
-        void emitDoublePrecisionInstruction(ARMWord op, int dd, int dn, int dm)
-        {
-            ASSERT((dd >= 0 && dd <= 31) && (dn >= 0 && dn <= 31) && (dm >= 0 && dm <= 31));
-            m_buffer.putInt(op | ((dd & 0xf) << 12) | ((dd & 0x10) << (22 - 4))
-                               | ((dn & 0xf) << 16) | ((dn & 0x10) << (7 - 4))
-                               | (dm & 0xf) | ((dm & 0x10) << (5 - 4)));
-        }
-
-        void emitSinglePrecisionInstruction(ARMWord op, int sd, int sn, int sm)
-        {
-            ASSERT((sd >= 0 && sd <= 31) && (sn >= 0 && sn <= 31) && (sm >= 0 && sm <= 31));
-            m_buffer.putInt(op | ((sd >> 1) << 12) | ((sd & 0x1) << 22)
-                               | ((sn >> 1) << 16) | ((sn & 0x1) << 7)
-                               | (sm >> 1) | ((sm & 0x1) << 5));
-        }
-
-        void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
-        }
-
-        void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
-        }
-
-        void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
-        }
-
-        void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
-        }
-
-        void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void add(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
-        }
-
-        void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
-        }
-
-        void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
-        }
-
-        void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
-        }
-
-        void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void tst(int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
-        }
-
-        void teq(int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
-        }
-
-        void cmp(int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
-        }
-
-        void cmn(int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
-        }
-
-        void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
-        }
-
-        void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void mov(int rd, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
-        }
-
-#if WTF_ARM_ARCH_AT_LEAST(7)
-        void movw(int rd, ARMWord op2, Condition cc = AL)
-        {
-            ASSERT((op2 | 0xf0fff) == 0xf0fff);
-            m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2);
-        }
-
-        void movt(int rd, ARMWord op2, Condition cc = AL)
-        {
-            ASSERT((op2 | 0xf0fff) == 0xf0fff);
-            m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2);
-        }
-#endif
-
-        void movs(int rd, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
-        }
-
-        void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
-        }
-
-        void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
-        }
-
-        void mvn(int rd, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
-        }
-
-        void mvns(int rd, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
-        }
-
-        void mul(int rd, int rn, int rm, Condition cc = AL)
-        {
-            m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
-        }
-
-        void muls(int rd, int rn, int rm, Condition cc = AL)
-        {
-            m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
-        }
-
-        void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
-        {
-            m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
-        }
-
-#if HAVE(ARM_IDIV_INSTRUCTIONS)
-        template<int datasize>
-        void sdiv(int rd, int rn, int rm, Condition cc = AL)
-        {
-            static_assert(datasize == 32, "sdiv datasize must be 32 for armv7s");
-            ASSERT(rd != ARMRegisters::pc);
-            ASSERT(rn != ARMRegisters::pc);
-            ASSERT(rm != ARMRegisters::pc);
-            m_buffer.putInt(toARMWord(cc) | SDIV | RN(rd) | RM(rn) | RS(rm));
-        }
-
-        void udiv(int rd, int rn, int rm, Condition cc = AL)
-        {
-            ASSERT(rd != ARMRegisters::pc);
-            ASSERT(rn != ARMRegisters::pc);
-            ASSERT(rm != ARMRegisters::pc);
-            m_buffer.putInt(toARMWord(cc) | UDIV | RN(rd) | RM(rn) | RS(rm));
-        }
-#endif
-
-        void vmov_f64(int dd, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
-        }
-
-        void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
-        }
-
-        void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
-        }
-
-        void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
-        }
-
-        void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
-        }
-
-        void vcmp_f64(int dd, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
-        }
-
-        void vsqrt_f64(int dd, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
-        }
-
-        void vabs_f64(int dd, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
-        }
-
-        void vneg_f64(int dd, int dm, Condition cc = AL)
-        {
-            emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
-        }
-
-        void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
-        {
-            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
-        }
-
-        void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
-        {
-            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
-        }
-
-        void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
-        }
-
-        void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
-        }
-
-        void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
-        }
-
-        void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
-        }
-
-        void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
-        }
-
-        void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
-        }
-
-        void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
-        }
-
-        void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
-        }
-
-        void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            ASSERT(op2 <= 0xff && rd <= 15);
-            /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
-            m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
-        }
-
-        void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
-        {
-            ASSERT(op2 <= 0xff && rd <= 15);
-            /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
-            m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2);
-        }
-
-        void push(int reg, Condition cc = AL)
-        {
-            ASSERT(ARMWord(reg) <= 0xf);
-            m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
-        }
-
-        void pop(int reg, Condition cc = AL)
-        {
-            ASSERT(ARMWord(reg) <= 0xf);
-            m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
-        }
-
-        inline void poke(int reg, Condition cc = AL)
-        {
-            dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
-        }
-
-        inline void peek(int reg, Condition cc = AL)
-        {
-            dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
-        }
-
-        void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
-        {
-            ASSERT(rt != rt2);
-            m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
-        }
-
-        void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
-        {
-            ASSERT(rt != rt2);
-            m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
-        }
-
-        void vmov_vfp32(int sn, int rt, Condition cc = AL)
-        {
-            ASSERT(rt <= 15);
-            emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0);
-        }
-
-        void vmov_arm32(int rt, int sn, Condition cc = AL)
-        {
-            ASSERT(rt <= 15);
-            emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0);
-        }
-
-        void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
-        {
-            ASSERT(!(sm & 0x1)); // sm must be divisible by 2
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
-        }
-
-        void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
-        {
-            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
-        }
-
-        void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
-        {
-            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm);
-        }
-
-        void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
-        {
-            ASSERT(dd <= 15 && sm <= 15);
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm);
-        }
-
-        void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
-        {
-            ASSERT(dd <= 15 && sm <= 15);
-            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm);
-        }
-
-        void vmrs_apsr(Condition cc = AL)
-        {
-            m_buffer.putInt(toARMWord(cc) | VMRS_APSR);
-        }
-
-        void clz(int rd, int rm, Condition cc = AL)
-        {
-            m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
-        }
-
-        void bkpt(ARMWord value)
-        {
-            m_buffer.putInt(BKPT | ((value & 0xff0) << 4) | (value & 0xf));
-        }
-
-        static bool isBkpt(void* address)
-        {
-            ARMWord expected = BKPT;
-            ARMWord immediateMask = (0xff0 << 4) | 0xf;
-            ARMWord candidateInstruction = *reinterpret_cast<ARMWord*>(address);
-            return (candidateInstruction & ~immediateMask) == expected;
-        }
-
-        void nop()
-        {
-            m_buffer.putInt(NOP);
-        }
-
-        template <typename CopyFunction>
-        static void fillNops(void* base, size_t size, CopyFunction copy)
-        {
-            UNUSED_PARAM(copy);
-            RELEASE_ASSERT(!(size % sizeof(int32_t)));
-
-            int32_t* ptr = static_cast<int32_t*>(base);
-            const size_t num32s = size / sizeof(int32_t);
-            const int32_t insn = NOP;
-            for (size_t i = 0; i < num32s; i++)
-                *ptr++ = insn;
-        }
-
-        void dmbSY()
-        {
-            m_buffer.putInt(DMB_SY);
-        }
-
-        void dmbISHST()
-        {
-            m_buffer.putInt(DMB_ISHST);
-        }
-
-        void bx(int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | BX, 0, 0, RM(rm));
-        }
-
-        AssemblerLabel blx(int rm, Condition cc = AL)
-        {
-            emitInstruction(toARMWord(cc) | BLX, 0, 0, RM(rm));
-            return m_buffer.label();
-        }
-
-        static ARMWord lsl(int reg, ARMWord value)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(value <= 0x1f);
-            return reg | (value << 7) | 0x00;
-        }
-
-        static ARMWord lsr(int reg, ARMWord value)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(value <= 0x1f);
-            return reg | (value << 7) | 0x20;
-        }
-
-        static ARMWord asr(int reg, ARMWord value)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(value <= 0x1f);
-            return reg | (value << 7) | 0x40;
-        }
-
-        static ARMWord lslRegister(int reg, int shiftReg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(shiftReg <= ARMRegisters::pc);
-            return reg | (shiftReg << 8) | 0x10;
-        }
-
-        static ARMWord lsrRegister(int reg, int shiftReg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(shiftReg <= ARMRegisters::pc);
-            return reg | (shiftReg << 8) | 0x30;
-        }
-
-        static ARMWord asrRegister(int reg, int shiftReg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            ASSERT(shiftReg <= ARMRegisters::pc);
-            return reg | (shiftReg << 8) | 0x50;
-        }
-
-        // General helpers
-
-        size_t codeSize() const
-        {
-            return m_buffer.codeSize();
-        }
-
-        void ensureSpace(int insnSpace, int constSpace)
-        {
-            m_buffer.ensureSpace(insnSpace, constSpace);
-        }
-
-        int sizeOfConstantPool()
-        {
-            return m_buffer.sizeOfConstantPool();
-        }
-
-        AssemblerLabel labelIgnoringWatchpoints()
-        {
-            m_buffer.ensureSpaceForAnyInstruction();
-            return m_buffer.label();
-        }
-
-        AssemblerLabel labelForWatchpoint()
-        {
-            m_buffer.ensureSpaceForAnyInstruction(maxJumpReplacementSize() / sizeof(ARMWord));
-            AssemblerLabel result = m_buffer.label();
-            if (result.m_offset != (m_indexOfTailOfLastWatchpoint - maxJumpReplacementSize()))
-                result = label();
-            m_indexOfTailOfLastWatchpoint = result.m_offset + maxJumpReplacementSize();
-            return label();
-        }
-
-        AssemblerLabel label()
-        {
-            AssemblerLabel result = labelIgnoringWatchpoints();
-            while (result.m_offset + 1 < m_indexOfTailOfLastWatchpoint) {
-                nop();
-                // The available number of instructions are ensured by labelForWatchpoint.
-                result = m_buffer.label();
-            }
-            return result;
-        }
-
-        AssemblerLabel align(int alignment)
-        {
-            while (!m_buffer.isAligned(alignment))
-                mov(ARMRegisters::r0, ARMRegisters::r0);
-
-            return label();
-        }
-
-        AssemblerLabel loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0)
-        {
-            ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
-            m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1));
-            ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
-            return m_buffer.label();
-        }
-
-        AssemblerLabel jmp(Condition cc = AL, int useConstantPool = 0)
-        {
-            return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
-        }
-
-        void prepareExecutableCopy(void* to);
-
-        unsigned debugOffset() { return m_buffer.debugOffset(); }
-
-        // DFG assembly helpers for moving data between fp and registers.
-        void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
-        {
-            vmov_arm64(rd1, rd2, rn);
-        }
-
-        void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
-        {
-            vmov_vfp64(rd, rn1, rn2);
-        }
-
-        // Patching helpers
-
-        static ARMWord* getLdrImmAddress(ARMWord* insn)
-        {
-            // Check for call
-            if ((*insn & LdrPcImmediateInstructionMask) != LdrPcImmediateInstruction) {
-                // Must be BLX
-                ASSERT((*insn & BlxInstructionMask) == BlxInstruction);
-                insn--;
-            }
-
-            // Must be an ldr ..., [pc +/- imm]
-            ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
-
-            ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetchOffset * sizeof(ARMWord);
-            if (*insn & DataTransferUp)
-                return reinterpret_cast<ARMWord*>(addr + (*insn & DataTransferOffsetMask));
-            return reinterpret_cast<ARMWord*>(addr - (*insn & DataTransferOffsetMask));
-        }
-
-        static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
-        {
-            // Must be an ldr ..., [pc +/- imm]
-            ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
-
-            if (*insn & 0x1)
-                return reinterpret_cast<ARMWord*>(constPool + ((*insn & DataTransferOffsetMask) >> 1));
-            return getLdrImmAddress(insn);
-        }
-
-        static void patchPointerInternal(intptr_t from, void* to)
-        {
-            ARMWord* insn = reinterpret_cast<ARMWord*>(from);
-            ARMWord* addr = getLdrImmAddress(insn);
-            *addr = reinterpret_cast<ARMWord>(to);
-        }
-
-        static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
-        {
-            value = (value << 1) + 1;
-            ASSERT(!(value & ~DataTransferOffsetMask));
-            return (load & ~DataTransferOffsetMask) | value;
-        }
-
-        static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr);
-
-        // Read pointers
-        static void* readPointer(void* from)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(from);
-            ARMWord* address = getLdrImmAddress(instruction);
-            return *reinterpret_cast<void**>(address);
-        }
-
-        // Patch pointers
-
-        static void linkPointer(void* code, AssemblerLabel from, void* to)
-        {
-            patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
-        }
-
-        static void repatchInt32(void* where, int32_t to)
-        {
-            patchPointerInternal(reinterpret_cast<intptr_t>(where), reinterpret_cast<void*>(to));
-        }
-
-        static void repatchCompact(void* where, int32_t value)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(where);
-            ASSERT((*instruction & 0x0f700000) == LoadUint32);
-            if (value >= 0)
-                *instruction = (*instruction & 0xff7ff000) | DataTransferUp | value;
-            else
-                *instruction = (*instruction & 0xff7ff000) | -value;
-            cacheFlush(instruction, sizeof(ARMWord));
-        }
-
-        static void repatchPointer(void* from, void* to)
-        {
-            patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
-        }
-
-        // Linkers
-        static intptr_t getAbsoluteJumpAddress(void* base, int offset = 0)
-        {
-            return reinterpret_cast<intptr_t>(base) + offset - sizeof(ARMWord);
-        }
-
-        void linkJump(AssemblerLabel from, AssemblerLabel to)
-        {
-            ARMWord* insn = reinterpret_cast<ARMWord*>(getAbsoluteJumpAddress(m_buffer.data(), from.m_offset));
-            ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
-            *addr = toARMWord(to.m_offset);
-        }
-
-        static void linkJump(void* code, AssemblerLabel from, void* to)
-        {
-            patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
-        }
-
-        static void relinkJump(void* from, void* to)
-        {
-            patchPointerInternal(getAbsoluteJumpAddress(from), to);
-        }
-
-        static void relinkJumpToNop(void* from)
-        {
-            relinkJump(from, from);
-        }
-
-        static void linkCall(void* code, AssemblerLabel from, void* to)
-        {
-            patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
-        }
-
-        static void relinkCall(void* from, void* to)
-        {
-            patchPointerInternal(getAbsoluteJumpAddress(from), to);
-        }
-
-        static void* readCallTarget(void* from)
-        {
-            return reinterpret_cast<void*>(readPointer(reinterpret_cast<void*>(getAbsoluteJumpAddress(from))));
-        }
-
-        static void replaceWithJump(void* instructionStart, void* to)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
-            intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + DefaultPrefetchOffset * sizeof(ARMWord));
-
-            if (!(difference & 1)) {
-                difference >>= 2;
-                if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
-                     // Direct branch.
-                     instruction[0] = B | AL | (difference & BranchOffsetMask);
-                     cacheFlush(instruction, sizeof(ARMWord));
-                     return;
-                }
-            }
-
-            // Load target.
-            instruction[0] = LoadUint32 | AL | RN(ARMRegisters::pc) | RD(ARMRegisters::pc) | 4;
-            instruction[1] = reinterpret_cast<ARMWord>(to);
-            cacheFlush(instruction, sizeof(ARMWord) * 2);
-        }
-
-        static ptrdiff_t maxJumpReplacementSize()
-        {
-            return sizeof(ARMWord) * 2;
-        }
-
-        static constexpr ptrdiff_t patchableJumpSize()
-        {
-            return sizeof(ARMWord) * 3;
-        }
-
-        static void replaceWithLoad(void* instructionStart)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
-            cacheFlush(instruction, sizeof(ARMWord));
-
-            ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
-            if ((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction) {
-                 *instruction = (*instruction & ~LdrOrAddInstructionMask) | LdrImmediateInstruction;
-                 cacheFlush(instruction, sizeof(ARMWord));
-            }
-        }
-
-        static void replaceWithAddressComputation(void* instructionStart)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
-            cacheFlush(instruction, sizeof(ARMWord));
-
-            ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
-            if ((*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction) {
-                 *instruction = (*instruction & ~LdrOrAddInstructionMask) | AddImmediateInstruction;
-                 cacheFlush(instruction, sizeof(ARMWord));
-            }
-        }
-
-        static void revertBranchPtrWithPatch(void* instructionStart, RegisterID rn, ARMWord imm)
-        {
-            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
-
-            ASSERT((instruction[2] & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
-            instruction[0] = toARMWord(AL) | ((instruction[2] & 0x0fff0fff) + sizeof(ARMWord)) | RD(ARMRegisters::S1);
-            *getLdrImmAddress(instruction) = imm;
-            instruction[1] = toARMWord(AL) | CMP | SetConditionalCodes | RN(rn) | RM(ARMRegisters::S1);
-            cacheFlush(instruction, 2 * sizeof(ARMWord));
-        }
-
-        // Address operations
-
-        static void* getRelocatedAddress(void* code, AssemblerLabel label)
-        {
-            return reinterpret_cast<void*>(reinterpret_cast<char*>(code) + label.m_offset);
-        }
-
-        // Address differences
-
-        static int getDifferenceBetweenLabels(AssemblerLabel a, AssemblerLabel b)
-        {
-            return b.m_offset - a.m_offset;
-        }
-
-        static unsigned getCallReturnOffset(AssemblerLabel call)
-        {
-            return call.m_offset;
-        }
-
-        // Handle immediates
-
-        static ARMWord getOp2(ARMWord imm);
-
-        // Fast case if imm is known to be between 0 and 0xff
-        static ARMWord getOp2Byte(ARMWord imm)
-        {
-            ASSERT(imm <= 0xff);
-            return Op2Immediate | imm;
-        }
-
-        static ARMWord getOp2Half(ARMWord imm)
-        {
-            ASSERT(imm <= 0xff);
-            return ImmediateForHalfWordTransfer | (imm & 0x0f) | ((imm & 0xf0) << 4);
-        }
-
-#if WTF_ARM_ARCH_AT_LEAST(7)
-        static ARMWord getImm16Op2(ARMWord imm)
-        {
-            if (imm <= 0xffff)
-                return (imm & 0xf000) << 4 | (imm & 0xfff);
-            return InvalidImmediate;
-        }
-#endif
-        ARMWord getImm(ARMWord imm, int tmpReg, bool invert = false);
-        void moveImm(ARMWord imm, int dest);
-        ARMWord encodeComplexImm(ARMWord imm, int dest);
-
-        // Memory load/store helpers
-
-        void dataTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, int32_t offset);
-        void baseIndexTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
-        void dataTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, int32_t offset);
-        void baseIndexTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
-        void dataTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, int32_t offset);
-        void baseIndexTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
-
-        // Constant pool hnadlers
-
-        static ARMWord placeConstantPoolBarrier(int offset)
-        {
-            offset = (offset - sizeof(ARMWord)) >> 2;
-            ASSERT((offset <= MaximumBranchOffsetDistance && offset >= MinimumBranchOffsetDistance));
-            return AL | B | (offset & BranchOffsetMask);
-        }
-
-#if OS(LINUX) && COMPILER(GCC_COMPATIBLE)
-        static inline void linuxPageFlush(uintptr_t begin, uintptr_t end)
-        {
-            asm volatile(
-                "push    {r7}\n"
-                "mov     r0, %0\n"
-                "mov     r1, %1\n"
-                "mov     r7, #0xf0000\n"
-                "add     r7, r7, #0x2\n"
-                "mov     r2, #0x0\n"
-                "svc     0x0\n"
-                "pop     {r7}\n"
-                :
-                : "r" (begin), "r" (end)
-                : "r0", "r1", "r2");
-        }
-#endif
-
-        static void cacheFlush(void* code, size_t size)
-        {
-#if OS(LINUX) && COMPILER(GCC_COMPATIBLE)
-            size_t page = pageSize();
-            uintptr_t current = reinterpret_cast<uintptr_t>(code);
-            uintptr_t end = current + size;
-            uintptr_t firstPageEnd = (current & ~(page - 1)) + page;
-
-            if (end <= firstPageEnd) {
-                linuxPageFlush(current, end);
-                return;
-            }
-
-            linuxPageFlush(current, firstPageEnd);
-
-            for (current = firstPageEnd; current + page < end; current += page)
-                linuxPageFlush(current, current + page);
-
-            linuxPageFlush(current, end);
-#else
-#error "The cacheFlush support is missing on this platform."
-#endif
-        }
-
-    private:
-        static ARMWord RM(int reg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            return reg;
-        }
-
-        static ARMWord RS(int reg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            return reg << 8;
-        }
-
-        static ARMWord RD(int reg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            return reg << 12;
-        }
-
-        static ARMWord RN(int reg)
-        {
-            ASSERT(reg <= ARMRegisters::pc);
-            return reg << 16;
-        }
-
-        static ARMWord getConditionalField(ARMWord i)
-        {
-            return i & ConditionalFieldMask;
-        }
-
-        static ARMWord toARMWord(Condition cc)
-        {
-            return static_cast<ARMWord>(cc);
-        }
-
-        static ARMWord toARMWord(uint32_t u)
-        {
-            return static_cast<ARMWord>(u);
-        }
-
-        int genInt(int reg, ARMWord imm, bool positive);
-
-        ARMBuffer m_buffer;
-        Jumps m_jumps;
-        uint32_t m_indexOfTailOfLastWatchpoint;
-    };
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
index ea107fb..b236a5c 100644 (file)
@@ -298,9 +298,7 @@ void LinkBuffer::linkCode(MacroAssembler& macroAssembler, void* ownerUID, JITCom
     ASSERT(m_code);
     AssemblerBuffer& buffer = macroAssembler.m_assembler.buffer();
     void* code = m_code.dataLocation();
-#if CPU(ARM_TRADITIONAL)
-    macroAssembler.m_assembler.prepareExecutableCopy(code);
-#elif CPU(ARM64)
+#if CPU(ARM64)
     RELEASE_ASSERT(roundUpToMultipleOf<Assembler::instructionSize>(code) == code);
 #endif
     performJITMemcpy(code, buffer.data(), buffer.codeSize());
@@ -400,23 +398,6 @@ void LinkBuffer::dumpCode(void* code, size_t size)
         
     for (unsigned i = 0; i < tsize; i++)
         dataLogF("\t.short\t0x%x\n", tcode[i]);
-#elif CPU(ARM_TRADITIONAL)
-    //   gcc -c jit.s
-    //   objdump -D jit.o
-    static unsigned codeCount = 0;
-    unsigned int* tcode = static_cast<unsigned int*>(code);
-    size_t tsize = size / sizeof(unsigned int);
-    char nameBuf[128];
-    snprintf(nameBuf, sizeof(nameBuf), "_jsc_jit%u", codeCount++);
-    dataLogF("\t.globl\t%s\n"
-            "\t.align 4\n"
-            "\t.code 32\n"
-            "\t.text\n"
-            "# %p\n"
-            "%s:\n", nameBuf, code, nameBuf);
-
-    for (unsigned i = 0; i < tsize; i++)
-        dataLogF("\t.long\t0x%x\n", tcode[i]);
 #endif
 }
 #endif
index cd1b545..3a72c27 100644 (file)
@@ -45,11 +45,6 @@ namespace JSC { typedef MacroAssemblerARMv7 MacroAssemblerBase; };
 #define TARGET_MACROASSEMBLER MacroAssemblerARM64
 #include "MacroAssemblerARM64.h"
 
-#elif CPU(ARM_TRADITIONAL)
-#define TARGET_ASSEMBLER ARMAssembler
-#define TARGET_MACROASSEMBLER MacroAssemblerARM
-#include "MacroAssemblerARM.h"
-
 #elif CPU(MIPS)
 #define TARGET_ASSEMBLER MIPSAssembler
 #define TARGET_MACROASSEMBLER MacroAssemblerMIPS
@@ -142,7 +137,7 @@ public:
     using MacroAssemblerBase::and32;
     using MacroAssemblerBase::branchAdd32;
     using MacroAssemblerBase::branchMul32;
-#if CPU(ARM64) || CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL) || CPU(X86_64) || CPU(MIPS)
+#if CPU(ARM64) || CPU(ARM_THUMB2) || CPU(X86_64) || CPU(MIPS)
     using MacroAssemblerBase::branchPtr;
 #endif
     using MacroAssemblerBase::branchSub32;
@@ -434,7 +429,6 @@ public:
         return PatchableJump(branch32WithPatch(cond, left, dataLabel, initialRightValue));
     }
 
-#if !CPU(ARM_TRADITIONAL)
     PatchableJump patchableJump()
     {
         return PatchableJump(jump());
@@ -460,7 +454,6 @@ public:
         return PatchableJump(branch32(cond, address, imm));
     }
 #endif
-#endif
 
     void jump(Label target)
     {
diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp b/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp
deleted file mode 100644 (file)
index 9574d6c..0000000
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Copyright (C) 2013-2017 Apple Inc.
- * Copyright (C) 2009 University of Szeged
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY UNIVERSITY OF SZEGED ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL UNIVERSITY OF SZEGED OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "config.h"
-
-#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
-#include "MacroAssembler.h"
-
-#include "ProbeContext.h"
-#include <wtf/InlineASM.h>
-
-#if OS(LINUX)
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <elf.h>
-#include <asm/hwcap.h>
-#endif
-
-namespace JSC {
-
-static bool isVFPPresent()
-{
-#if OS(LINUX)
-    int fd = open("/proc/self/auxv", O_RDONLY);
-    if (fd != -1) {
-        Elf32_auxv_t aux;
-        while (read(fd, &aux, sizeof(Elf32_auxv_t))) {
-            if (aux.a_type == AT_HWCAP) {
-                close(fd);
-                return aux.a_un.a_val & HWCAP_VFP;
-            }
-        }
-        close(fd);
-    }
-#endif // OS(LINUX)
-
-#if (COMPILER(GCC_COMPATIBLE) && defined(__VFP_FP__))
-    return true;
-#else
-    return false;
-#endif
-}
-
-const bool MacroAssemblerARM::s_isVFPPresent = isVFPPresent();
-
-#if CPU(ARMV5_OR_LOWER)
-/* On ARMv5 and below, natural alignment is required. */
-void MacroAssemblerARM::load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
-{
-    ARMWord op2;
-
-    ASSERT(address.scale >= 0 && address.scale <= 3);
-    op2 = m_assembler.lsl(address.index, static_cast<int>(address.scale));
-
-    if (address.offset >= 0 && address.offset + 0x2 <= 0xff) {
-        m_assembler.add(ARMRegisters::S0, address.base, op2);
-        m_assembler.halfDtrUp(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset));
-        m_assembler.halfDtrUp(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2));
-    } else if (address.offset < 0 && address.offset >= -0xff) {
-        m_assembler.add(ARMRegisters::S0, address.base, op2);
-        m_assembler.halfDtrDown(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset));
-        m_assembler.halfDtrDown(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2));
-    } else {
-        m_assembler.moveImm(address.offset, ARMRegisters::S0);
-        m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, op2);
-        m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0);
-        m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2);
-        m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0);
-    }
-    m_assembler.orr(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16));
-}
-#endif // CPU(ARMV5_OR_LOWER)
-
-#if ENABLE(MASM_PROBE)
-
-extern "C" void ctiMasmProbeTrampoline();
-
-using namespace ARMRegisters;
-
-#if COMPILER(GCC_COMPATIBLE)
-
-// The following are offsets for Probe::State fields accessed
-// by the ctiMasmProbeTrampoline stub.
-
-#define PTR_SIZE 4
-#define PROBE_PROBE_FUNCTION_OFFSET (0 * PTR_SIZE)
-#define PROBE_ARG_OFFSET (1 * PTR_SIZE)
-#define PROBE_INIT_STACK_FUNCTION_OFFSET (2 * PTR_SIZE)
-#define PROBE_INIT_STACK_ARG_OFFSET (3 * PTR_SIZE)
-
-#define PROBE_FIRST_GPREG_OFFSET (4 * PTR_SIZE)
-
-#define GPREG_SIZE 4
-#define PROBE_CPU_R0_OFFSET (PROBE_FIRST_GPREG_OFFSET + (0 * GPREG_SIZE))
-#define PROBE_CPU_R1_OFFSET (PROBE_FIRST_GPREG_OFFSET + (1 * GPREG_SIZE))
-#define PROBE_CPU_R2_OFFSET (PROBE_FIRST_GPREG_OFFSET + (2 * GPREG_SIZE))
-#define PROBE_CPU_R3_OFFSET (PROBE_FIRST_GPREG_OFFSET + (3 * GPREG_SIZE))
-#define PROBE_CPU_R4_OFFSET (PROBE_FIRST_GPREG_OFFSET + (4 * GPREG_SIZE))
-#define PROBE_CPU_R5_OFFSET (PROBE_FIRST_GPREG_OFFSET + (5 * GPREG_SIZE))
-#define PROBE_CPU_R6_OFFSET (PROBE_FIRST_GPREG_OFFSET + (6 * GPREG_SIZE))
-#define PROBE_CPU_R7_OFFSET (PROBE_FIRST_GPREG_OFFSET + (7 * GPREG_SIZE))
-#define PROBE_CPU_R8_OFFSET (PROBE_FIRST_GPREG_OFFSET + (8 * GPREG_SIZE))
-#define PROBE_CPU_R9_OFFSET (PROBE_FIRST_GPREG_OFFSET + (9 * GPREG_SIZE))
-#define PROBE_CPU_R10_OFFSET (PROBE_FIRST_GPREG_OFFSET + (10 * GPREG_SIZE))
-#define PROBE_CPU_R11_OFFSET (PROBE_FIRST_GPREG_OFFSET + (11 * GPREG_SIZE))
-#define PROBE_CPU_IP_OFFSET (PROBE_FIRST_GPREG_OFFSET + (12 * GPREG_SIZE))
-#define PROBE_CPU_SP_OFFSET (PROBE_FIRST_GPREG_OFFSET + (13 * GPREG_SIZE))
-#define PROBE_CPU_LR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (14 * GPREG_SIZE))
-#define PROBE_CPU_PC_OFFSET (PROBE_FIRST_GPREG_OFFSET + (15 * GPREG_SIZE))
-
-#define PROBE_CPU_APSR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (16 * GPREG_SIZE))
-#define PROBE_CPU_FPSCR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (17 * GPREG_SIZE))
-
-#define PROBE_FIRST_FPREG_OFFSET (PROBE_FIRST_GPREG_OFFSET + (18 * GPREG_SIZE))
-
-#define FPREG_SIZE 8
-#define PROBE_CPU_D0_OFFSET (PROBE_FIRST_FPREG_OFFSET + (0 * FPREG_SIZE))
-#define PROBE_CPU_D1_OFFSET (PROBE_FIRST_FPREG_OFFSET + (1 * FPREG_SIZE))
-#define PROBE_CPU_D2_OFFSET (PROBE_FIRST_FPREG_OFFSET + (2 * FPREG_SIZE))
-#define PROBE_CPU_D3_OFFSET (PROBE_FIRST_FPREG_OFFSET + (3 * FPREG_SIZE))
-#define PROBE_CPU_D4_OFFSET (PROBE_FIRST_FPREG_OFFSET + (4 * FPREG_SIZE))
-#define PROBE_CPU_D5_OFFSET (PROBE_FIRST_FPREG_OFFSET + (5 * FPREG_SIZE))
-#define PROBE_CPU_D6_OFFSET (PROBE_FIRST_FPREG_OFFSET + (6 * FPREG_SIZE))
-#define PROBE_CPU_D7_OFFSET (PROBE_FIRST_FPREG_OFFSET + (7 * FPREG_SIZE))
-#define PROBE_CPU_D8_OFFSET (PROBE_FIRST_FPREG_OFFSET + (8 * FPREG_SIZE))
-#define PROBE_CPU_D9_OFFSET (PROBE_FIRST_FPREG_OFFSET + (9 * FPREG_SIZE))
-#define PROBE_CPU_D10_OFFSET (PROBE_FIRST_FPREG_OFFSET + (10 * FPREG_SIZE))
-#define PROBE_CPU_D11_OFFSET (PROBE_FIRST_FPREG_OFFSET + (11 * FPREG_SIZE))
-#define PROBE_CPU_D12_OFFSET (PROBE_FIRST_FPREG_OFFSET + (12 * FPREG_SIZE))
-#define PROBE_CPU_D13_OFFSET (PROBE_FIRST_FPREG_OFFSET + (13 * FPREG_SIZE))
-#define PROBE_CPU_D14_OFFSET (PROBE_FIRST_FPREG_OFFSET + (14 * FPREG_SIZE))
-#define PROBE_CPU_D15_OFFSET (PROBE_FIRST_FPREG_OFFSET + (15 * FPREG_SIZE))
-
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-#define PROBE_CPU_D16_OFFSET (PROBE_FIRST_FPREG_OFFSET + (16 * FPREG_SIZE))
-#define PROBE_CPU_D17_OFFSET (PROBE_FIRST_FPREG_OFFSET + (17 * FPREG_SIZE))
-#define PROBE_CPU_D18_OFFSET (PROBE_FIRST_FPREG_OFFSET + (18 * FPREG_SIZE))
-#define PROBE_CPU_D19_OFFSET (PROBE_FIRST_FPREG_OFFSET + (19 * FPREG_SIZE))
-#define PROBE_CPU_D20_OFFSET (PROBE_FIRST_FPREG_OFFSET + (20 * FPREG_SIZE))
-#define PROBE_CPU_D21_OFFSET (PROBE_FIRST_FPREG_OFFSET + (21 * FPREG_SIZE))
-#define PROBE_CPU_D22_OFFSET (PROBE_FIRST_FPREG_OFFSET + (22 * FPREG_SIZE))
-#define PROBE_CPU_D23_OFFSET (PROBE_FIRST_FPREG_OFFSET + (23 * FPREG_SIZE))
-#define PROBE_CPU_D24_OFFSET (PROBE_FIRST_FPREG_OFFSET + (24 * FPREG_SIZE))
-#define PROBE_CPU_D25_OFFSET (PROBE_FIRST_FPREG_OFFSET + (25 * FPREG_SIZE))
-#define PROBE_CPU_D26_OFFSET (PROBE_FIRST_FPREG_OFFSET + (26 * FPREG_SIZE))
-#define PROBE_CPU_D27_OFFSET (PROBE_FIRST_FPREG_OFFSET + (27 * FPREG_SIZE))
-#define PROBE_CPU_D28_OFFSET (PROBE_FIRST_FPREG_OFFSET + (28 * FPREG_SIZE))
-#define PROBE_CPU_D29_OFFSET (PROBE_FIRST_FPREG_OFFSET + (29 * FPREG_SIZE))
-#define PROBE_CPU_D30_OFFSET (PROBE_FIRST_FPREG_OFFSET + (30 * FPREG_SIZE))
-#define PROBE_CPU_D31_OFFSET (PROBE_FIRST_FPREG_OFFSET + (31 * FPREG_SIZE))
-
-#define PROBE_SIZE (PROBE_FIRST_FPREG_OFFSET + (32 * FPREG_SIZE))
-#else
-#define PROBE_SIZE (PROBE_FIRST_FPREG_OFFSET + (16 * FPREG_SIZE))
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-
-#define OUT_SIZE GPREG_SIZE
-
-// These ASSERTs remind you that if you change the layout of Probe::State,
-// you need to change ctiMasmProbeTrampoline offsets above to match.
-#define PROBE_OFFSETOF(x) offsetof(struct Probe::State, x)
-static_assert(PROBE_OFFSETOF(probeFunction) == PROBE_PROBE_FUNCTION_OFFSET, "Probe::State::probeFunction's offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(arg) == PROBE_ARG_OFFSET, "Probe::State::arg's offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(initializeStackFunction) == PROBE_INIT_STACK_FUNCTION_OFFSET, "Probe::State::initializeStackFunction's offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(initializeStackArg) == PROBE_INIT_STACK_ARG_OFFSET, "Probe::State::initializeStackArg's offset matches ctiMasmProbeTrampoline");
-
-static_assert(!(PROBE_CPU_R0_OFFSET & 0x3), "Probe::State::cpu.gprs[r0]'s offset should be 4 byte aligned");
-
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r0]) == PROBE_CPU_R0_OFFSET, "Probe::State::cpu.gprs[r0]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r1]) == PROBE_CPU_R1_OFFSET, "Probe::State::cpu.gprs[r1]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r2]) == PROBE_CPU_R2_OFFSET, "Probe::State::cpu.gprs[r2]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r3]) == PROBE_CPU_R3_OFFSET, "Probe::State::cpu.gprs[r3]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r4]) == PROBE_CPU_R4_OFFSET, "Probe::State::cpu.gprs[r4]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r5]) == PROBE_CPU_R5_OFFSET, "Probe::State::cpu.gprs[r5]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r6]) == PROBE_CPU_R6_OFFSET, "Probe::State::cpu.gprs[r6]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r7]) == PROBE_CPU_R7_OFFSET, "Probe::State::cpu.gprs[r7]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r8]) == PROBE_CPU_R8_OFFSET, "Probe::State::cpu.gprs[r8]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r9]) == PROBE_CPU_R9_OFFSET, "Probe::State::cpu.gprs[r9]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r10]) == PROBE_CPU_R10_OFFSET, "Probe::State::cpu.gprs[r10]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::r11]) == PROBE_CPU_R11_OFFSET, "Probe::State::cpu.gprs[r11]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::ip]) == PROBE_CPU_IP_OFFSET, "Probe::State::cpu.gprs[ip]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::sp]) == PROBE_CPU_SP_OFFSET, "Probe::State::cpu.gprs[sp]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::lr]) == PROBE_CPU_LR_OFFSET, "Probe::State::cpu.gprs[lr]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.gprs[ARMRegisters::pc]) == PROBE_CPU_PC_OFFSET, "Probe::State::cpu.gprs[pc]'s offset matches ctiMasmProbeTrampoline");
-
-static_assert(PROBE_OFFSETOF(cpu.sprs[ARMRegisters::apsr]) == PROBE_CPU_APSR_OFFSET, "Probe::State::cpu.sprs[apsr]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.sprs[ARMRegisters::fpscr]) == PROBE_CPU_FPSCR_OFFSET, "Probe::State::cpu.sprs[fpscr]'s offset matches ctiMasmProbeTrampoline");
-
-static_assert(!(PROBE_CPU_D0_OFFSET & 0x7), "Probe::State::cpu.fprs[d0]'s offset should be 8 byte aligned");
-
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d0]) == PROBE_CPU_D0_OFFSET, "Probe::State::cpu.fprs[d0]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d1]) == PROBE_CPU_D1_OFFSET, "Probe::State::cpu.fprs[d1]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d2]) == PROBE_CPU_D2_OFFSET, "Probe::State::cpu.fprs[d2]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d3]) == PROBE_CPU_D3_OFFSET, "Probe::State::cpu.fprs[d3]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d4]) == PROBE_CPU_D4_OFFSET, "Probe::State::cpu.fprs[d4]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d5]) == PROBE_CPU_D5_OFFSET, "Probe::State::cpu.fprs[d5]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d6]) == PROBE_CPU_D6_OFFSET, "Probe::State::cpu.fprs[d6]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d7]) == PROBE_CPU_D7_OFFSET, "Probe::State::cpu.fprs[d7]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d8]) == PROBE_CPU_D8_OFFSET, "Probe::State::cpu.fprs[d8]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d9]) == PROBE_CPU_D9_OFFSET, "Probe::State::cpu.fprs[d9]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d10]) == PROBE_CPU_D10_OFFSET, "Probe::State::cpu.fprs[d10]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d11]) == PROBE_CPU_D11_OFFSET, "Probe::State::cpu.fprs[d11]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d12]) == PROBE_CPU_D12_OFFSET, "Probe::State::cpu.fprs[d12]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d13]) == PROBE_CPU_D13_OFFSET, "Probe::State::cpu.fprs[d13]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d14]) == PROBE_CPU_D14_OFFSET, "Probe::State::cpu.fprs[d14]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d15]) == PROBE_CPU_D15_OFFSET, "Probe::State::cpu.fprs[d15]'s offset matches ctiMasmProbeTrampoline");
-
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d16]) == PROBE_CPU_D16_OFFSET, "Probe::State::cpu.fprs[d16]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d17]) == PROBE_CPU_D17_OFFSET, "Probe::State::cpu.fprs[d17]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d18]) == PROBE_CPU_D18_OFFSET, "Probe::State::cpu.fprs[d18]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d19]) == PROBE_CPU_D19_OFFSET, "Probe::State::cpu.fprs[d19]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d20]) == PROBE_CPU_D20_OFFSET, "Probe::State::cpu.fprs[d20]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d21]) == PROBE_CPU_D21_OFFSET, "Probe::State::cpu.fprs[d21]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d22]) == PROBE_CPU_D22_OFFSET, "Probe::State::cpu.fprs[d22]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d23]) == PROBE_CPU_D23_OFFSET, "Probe::State::cpu.fprs[d23]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d24]) == PROBE_CPU_D24_OFFSET, "Probe::State::cpu.fprs[d24]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d25]) == PROBE_CPU_D25_OFFSET, "Probe::State::cpu.fprs[d25]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d26]) == PROBE_CPU_D26_OFFSET, "Probe::State::cpu.fprs[d26]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d27]) == PROBE_CPU_D27_OFFSET, "Probe::State::cpu.fprs[d27]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d28]) == PROBE_CPU_D28_OFFSET, "Probe::State::cpu.fprs[d28]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d29]) == PROBE_CPU_D29_OFFSET, "Probe::State::cpu.fprs[d29]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d30]) == PROBE_CPU_D30_OFFSET, "Probe::State::cpu.fprs[d30]'s offset matches ctiMasmProbeTrampoline");
-static_assert(PROBE_OFFSETOF(cpu.fprs[ARMRegisters::d31]) == PROBE_CPU_D31_OFFSET, "Probe::State::cpu.fprs[d31]'s offset matches ctiMasmProbeTrampoline");
-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-
-static_assert(sizeof(Probe::State) == PROBE_SIZE, "Probe::State's size matches ctiMasmProbeTrampoline");
-#undef PROBE_OFFSETOF
-
-struct IncomingRecord {
-    uintptr_t lr;
-    uintptr_t ip;
-    uintptr_t r6;
-    uintptr_t r0;
-    uintptr_t r1;
-    uintptr_t r2;
-};
-
-#define IN_LR_OFFSET (0 * PTR_SIZE)
-#define IN_IP_OFFSET (1 * PTR_SIZE)
-#define IN_R6_OFFSET (2 * PTR_SIZE)
-#define IN_R0_OFFSET (3 * PTR_SIZE)
-#define IN_R1_OFFSET (4 * PTR_SIZE)
-#define IN_R2_OFFSET (5 * PTR_SIZE)
-#define IN_SIZE      (6 * PTR_SIZE)
-
-static_assert(IN_LR_OFFSET == offsetof(IncomingRecord, lr), "IN_LR_OFFSET is incorrect");
-static_assert(IN_IP_OFFSET == offsetof(IncomingRecord, ip), "IN_IP_OFFSET is incorrect");
-static_assert(IN_R6_OFFSET == offsetof(IncomingRecord, r6), "IN_R6_OFFSET is incorrect");
-static_assert(IN_R0_OFFSET == offsetof(IncomingRecord, r0), "IN_R0_OFFSET is incorrect");
-static_assert(IN_R1_OFFSET == offsetof(IncomingRecord, r1), "IN_R1_OFFSET is incorrect");
-static_assert(IN_R2_OFFSET == offsetof(IncomingRecord, r2), "IN_R2_OFFSET is incorrect");
-static_assert(IN_SIZE == sizeof(IncomingRecord), "IN_SIZE is incorrect");
-
-asm (
-    ".text" "\n"
-    ".globl " SYMBOL_STRING(ctiMasmProbeTrampoline) "\n"
-    HIDE_SYMBOL(ctiMasmProbeTrampoline) "\n"
-    INLINE_ARM_FUNCTION(ctiMasmProbeTrampoline) "\n"
-    SYMBOL_STRING(ctiMasmProbeTrampoline) ":" "\n"
-
-    // MacroAssemblerARMv7::probe() has already generated code to store some values.
-    // The top of stack now contains the IncomingRecord.
-    //
-    // Incoming register values:
-    //     r0: probe function
-    //     r1: probe arg
-    //     r2: Probe::executeProbe
-    //     r6: scratch
-    //     ip: scratch, was ctiMasmProbeTrampoline
-    //     lr: return address
-
-    "mov       ip, sp" "\n"
-    "mov       r6, sp" "\n"
-    "sub       r6, r6, #" STRINGIZE_VALUE_OF(PROBE_SIZE + OUT_SIZE) "\n"
-
-    // The ARM EABI specifies that the stack needs to be 16 byte aligned.
-    "bic       r6, r6, #0xf" "\n"
-    "mov       sp, r6" "\n" // Set the sp to protect the Probe::State from interrupts before we initialize it.
-
-    "str       r0, [sp, #" STRINGIZE_VALUE_OF(PROBE_PROBE_FUNCTION_OFFSET) "]" "\n"
-    "str       r1, [sp, #" STRINGIZE_VALUE_OF(PROBE_ARG_OFFSET) "]" "\n"
-    "str       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n"
-
-    "add       r0, ip, #" STRINGIZE_VALUE_OF(IN_SIZE) "\n"
-    "str       r0, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n"
-
-    "add       lr, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R3_OFFSET) "\n"
-    "stmia     lr, { r3-r5 }" "\n"
-    "add       lr, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R7_OFFSET) "\n"
-    "stmia     lr, { r7-r11 }" "\n"
-    "mrs       lr, APSR" "\n"
-    "str       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n"
-    "vmrs      lr, FPSCR" "\n"
-    "str       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_FPSCR_OFFSET) "]" "\n"
-
-    "ldr       r4, [ip, #" STRINGIZE_VALUE_OF(IN_LR_OFFSET) "]" "\n"
-    "ldr       r5, [ip, #" STRINGIZE_VALUE_OF(IN_IP_OFFSET) "]" "\n"
-    "ldr       r6, [ip, #" STRINGIZE_VALUE_OF(IN_R6_OFFSET) "]" "\n"
-    "ldr       r7, [ip, #" STRINGIZE_VALUE_OF(IN_R0_OFFSET) "]" "\n"
-    "ldr       r8, [ip, #" STRINGIZE_VALUE_OF(IN_R1_OFFSET) "]" "\n"
-    "ldr       r9, [ip, #" STRINGIZE_VALUE_OF(IN_R2_OFFSET) "]" "\n"
-    "str       r4, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n"
-    "str       r5, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n"
-    "str       r6, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R6_OFFSET) "]" "\n"
-    "str       r7, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R0_OFFSET) "]" "\n"
-    "str       r8, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R1_OFFSET) "]" "\n"
-    "str       r9, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R2_OFFSET) "]" "\n"
-
-    "add       ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D0_OFFSET) "\n"
-    "vstmia.64 ip!, { d0-d15 }" "\n"
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-    "vstmia.64 ip!, { d16-d31 }" "\n"
-#endif
-
-    // r5 is a callee saved register. We'll use it for preserving the Probe::State*.
-    // https://stackoverflow.com/questions/261419/arm-to-c-calling-convention-registers-to-save#261496
-    "mov       r5, sp" "\n"
-
-    "mov       r0, sp" "\n" // the Probe::State* arg.
-    "blx       r2" "\n" // Call Probe::executeProbe.
-
-    // Make sure the Probe::State is entirely below the result stack pointer so
-    // that register values are still preserved when we call the initializeStack
-    // function.
-    "ldr       r1, [r5, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" // Result sp.
-    "add       r2, r5, #" STRINGIZE_VALUE_OF(PROBE_SIZE + OUT_SIZE) "\n" // End of ProveContext + buffer.
-    "cmp       r1, r2" "\n"
-    "bge     " LOCAL_LABEL_STRING(ctiMasmProbeTrampolineProbeStateIsSafe) "\n"
-
-    // Allocate a safe place on the stack below the result stack pointer to stash the Probe::State.
-    "sub       r1, r1, #" STRINGIZE_VALUE_OF(PROBE_SIZE + OUT_SIZE) "\n"
-    "bic       r1, r1, #0xf" "\n" // The ARM EABI specifies that the stack needs to be 16 byte aligned.
-    "mov       sp, r1" "\n" // Set the new sp to protect that memory from interrupts before we copy the Probe::State.
-
-    // Copy the Probe::State to the safe place.
-    // Note: we have to copy from low address to higher address because we're moving the
-    // Probe::State to a lower address.
-    "add       r7, r5, #" STRINGIZE_VALUE_OF(PROBE_SIZE) "\n"
-
-    LOCAL_LABEL_STRING(ctiMasmProbeTrampolineCopyLoop) ":" "\n"
-    "ldr       r3, [r5], #4" "\n"
-    "ldr       r4, [r5], #4" "\n"
-    "str       r3, [r1], #4" "\n"
-    "str       r4, [r1], #4" "\n"
-    "cmp       r5, r7" "\n"
-    "blt     " LOCAL_LABEL_STRING(ctiMasmProbeTrampolineCopyLoop) "\n"
-
-    "mov       r5, sp" "\n"
-
-    // Call initializeStackFunction if present.
-    LOCAL_LABEL_STRING(ctiMasmProbeTrampolineProbeStateIsSafe) ":" "\n"
-    "ldr       r2, [r5, #" STRINGIZE_VALUE_OF(PROBE_INIT_STACK_FUNCTION_OFFSET) "]" "\n"
-    "cmp       r2, #0" "\n"
-    "beq     " LOCAL_LABEL_STRING(ctiMasmProbeTrampolineRestoreRegisters) "\n"
-
-    "mov       r0, r5" "\n" // Set the Probe::State* arg.
-    "blx       r2" "\n" // Call the initializeStackFunction (loaded into r2 above).
-
-    LOCAL_LABEL_STRING(ctiMasmProbeTrampolineRestoreRegisters) ":" "\n"
-
-    "mov       sp, r5" "\n" // Ensure that sp points to the Probe::State*.
-
-    // To enable probes to modify register state, we copy all registers
-    // out of the Probe::State before returning.
-
-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
-    "add       ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D31_OFFSET + FPREG_SIZE) "\n"
-    "vldmdb.64 ip!, { d16-d31 }" "\n"
-    "vldmdb.64 ip!, { d0-d15 }" "\n"
-#else
-    "add       ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D15_OFFSET + FPREG_SIZE) "\n"
-    "vldmdb.64 ip!, { d0-d15 }" "\n"
-#endif
-
-    "add       ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R11_OFFSET + GPREG_SIZE) "\n"
-    "ldmdb     ip, { r0-r11 }" "\n"
-    "ldr       ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_FPSCR_OFFSET) "]" "\n"
-    "vmsr      FPSCR, ip" "\n"
-
-    // There are 5 more registers left to restore: ip, sp, lr, pc, and apsr.
-
-    // Set up the restore area for sp and pc.
-    "ldr       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n"
-
-    // Push the pc on to the restore area.
-    "ldr       ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n"
-    "sub       lr, lr, #" STRINGIZE_VALUE_OF(OUT_SIZE) "\n"
-    "str       ip, [lr]" "\n"
-    // Point sp to the restore area.
-    "str       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n"
-
-    // All done with math i.e. won't trash the status register (apsr) and don't need
-    // scratch registers (lr and ip) anymore. Restore apsr, lr, and ip.
-    "ldr       ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n"
-    "msr       APSR, ip" "\n"
-    "ldr       lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n"
-    "ldr       ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n"
-
-    // Restore the sp and pc.
-    "ldr       sp, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n"
-    "pop       { pc }" "\n"
-);
-#endif // COMPILER(GCC_COMPATIBLE)
-
-void MacroAssembler::probe(Probe::Function function, void* arg)
-{
-    sub32(TrustedImm32(sizeof(IncomingRecord)), sp);
-
-    store32(lr, Address(sp, offsetof(IncomingRecord, lr)));
-    store32(ip, Address(sp, offsetof(IncomingRecord, ip)));
-    store32(r6, Address(sp, offsetof(IncomingRecord, r6))); // S0 == r6.
-    store32(r0, Address(sp, offsetof(IncomingRecord, r0)));
-    store32(r1, Address(sp, offsetof(IncomingRecord, r1)));
-    store32(r2, Address(sp, offsetof(IncomingRecord, r2)));
-    // The following uses RegisterID::S0. So, they must come after we preserve S0 above.
-    move(TrustedImmPtr(reinterpret_cast<void*>(function)), r0);
-    move(TrustedImmPtr(arg), r1);
-    move(TrustedImmPtr(reinterpret_cast<void*>(Probe::executeProbe)), r2);
-    move(TrustedImmPtr(reinterpret_cast<void*>(ctiMasmProbeTrampoline)), ip);
-    m_assembler.blx(ip);
-}
-#endif // ENABLE(MASM_PROBE)
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h
deleted file mode 100644 (file)
index fa4df51..0000000
+++ /dev/null
@@ -1,1676 +0,0 @@
-/*
- * Copyright (C) 2008-2018 Apple Inc.
- * Copyright (C) 2009, 2010 University of Szeged
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#pragma once
-
-#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
-
-#include "ARMAssembler.h"
-#include "AbstractMacroAssembler.h"
-
-namespace JSC {
-
-using Assembler = TARGET_ASSEMBLER;
-
-class MacroAssemblerARM : public AbstractMacroAssembler<Assembler> {
-    static const int DoubleConditionMask = 0x0f;
-    static const int DoubleConditionBitSpecial = 0x10;
-    COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
-public:
-    static const unsigned numGPRs = 16;
-    static const unsigned numFPRs = 16;
-    
-    typedef ARMRegisters::FPRegisterID FPRegisterID;
-
-    static const RegisterID dataTempRegister = ARMRegisters::ip;
-    static const RegisterID addressTempRegister = ARMRegisters::r6;
-
-    static const ARMRegisters::FPRegisterID fpTempRegister = ARMRegisters::d7;
-
-    enum RelationalCondition {
-        Equal = ARMAssembler::EQ,
-        NotEqual = ARMAssembler::NE,
-        Above = ARMAssembler::HI,
-        AboveOrEqual = ARMAssembler::CS,
-        Below = ARMAssembler::CC,
-        BelowOrEqual = ARMAssembler::LS,
-        GreaterThan = ARMAssembler::GT,
-        GreaterThanOrEqual = ARMAssembler::GE,
-        LessThan = ARMAssembler::LT,
-        LessThanOrEqual = ARMAssembler::LE
-    };
-
-    enum ResultCondition {
-        Overflow = ARMAssembler::VS,
-        Signed = ARMAssembler::MI,
-        PositiveOrZero = ARMAssembler::PL,
-        Zero = ARMAssembler::EQ,
-        NonZero = ARMAssembler::NE
-    };
-
-    enum DoubleCondition {
-        // These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
-        DoubleEqual = ARMAssembler::EQ,
-        DoubleNotEqual = ARMAssembler::NE | DoubleConditionBitSpecial,
-        DoubleGreaterThan = ARMAssembler::GT,
-        DoubleGreaterThanOrEqual = ARMAssembler::GE,
-        DoubleLessThan = ARMAssembler::CC,
-        DoubleLessThanOrEqual = ARMAssembler::LS,
-        // If either operand is NaN, these conditions always evaluate to true.
-        DoubleEqualOrUnordered = ARMAssembler::EQ | DoubleConditionBitSpecial,
-        DoubleNotEqualOrUnordered = ARMAssembler::NE,
-        DoubleGreaterThanOrUnordered = ARMAssembler::HI,
-        DoubleGreaterThanOrEqualOrUnordered = ARMAssembler::CS,
-        DoubleLessThanOrUnordered = ARMAssembler::LT,
-        DoubleLessThanOrEqualOrUnordered = ARMAssembler::LE,
-    };
-
-    static const RegisterID stackPointerRegister = ARMRegisters::sp;
-    static const RegisterID framePointerRegister = ARMRegisters::fp;
-    static const RegisterID linkRegister = ARMRegisters::lr;
-
-    static const Scale ScalePtr = TimesFour;
-
-    void add32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.adds(dest, dest, src);
-    }
-
-    void add32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        m_assembler.adds(dest, op1, op2);
-    }
-
-    void add32(TrustedImm32 imm, Address address)
-    {
-        load32(address, dataTempRegister);
-        add32(imm, dataTempRegister);
-        store32(dataTempRegister, address);
-    }
-
-    void add32(TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void add32(AbsoluteAddress src, RegisterID dest)
-    {
-        move(TrustedImmPtr(src.m_ptr), dataTempRegister);
-        m_assembler.dtrUp(ARMAssembler::LoadUint32, dataTempRegister, dataTempRegister, 0);
-        add32(dataTempRegister, dest);
-    }
-
-    void add32(Address src, RegisterID dest)
-    {
-        load32(src, dataTempRegister);
-        add32(dataTempRegister, dest);
-    }
-
-    void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void getEffectiveAddress(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.add(dest, address.base, m_assembler.lsl(address.index, static_cast<int>(address.scale)));
-        if (address.offset)
-            add32(TrustedImm32(address.offset), dest);
-    }
-
-    void and32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.bitAnds(dest, dest, src);
-    }
-
-    void and32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        m_assembler.bitAnds(dest, op1, op2);
-    }
-
-    void and32(TrustedImm32 imm, RegisterID dest)
-    {
-        ARMWord w = m_assembler.getImm(imm.m_value, addressTempRegister, true);
-        if (w & ARMAssembler::Op2InvertedImmediate)
-            m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
-        else
-            m_assembler.bitAnds(dest, dest, w);
-    }
-
-    void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
-    {
-        ARMWord w = m_assembler.getImm(imm.m_value, addressTempRegister, true);
-        if (w & ARMAssembler::Op2InvertedImmediate)
-            m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
-        else
-            m_assembler.bitAnds(dest, src, w);
-    }
-
-    void and32(Address src, RegisterID dest)
-    {
-        load32(src, dataTempRegister);
-        and32(dataTempRegister, dest);
-    }
-
-    void and16(Address src, RegisterID dest)
-    {
-        load16(src, dataTempRegister);
-        and32(dataTempRegister, dest);
-    }
-
-    void lshift32(RegisterID shiftAmount, RegisterID dest)
-    {
-        lshift32(dest, shiftAmount, dest);
-    }
-
-    void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
-    {
-        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
-        m_assembler.bitAnd(addressTempRegister, shiftAmount, w);
-
-        m_assembler.movs(dest, m_assembler.lslRegister(src, addressTempRegister));
-    }
-
-    void lshift32(TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
-    }
-
-    void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
-    }
-
-    void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        if (op2 == dest) {
-            if (op1 == dest) {
-                move(op2, addressTempRegister);
-                op2 = addressTempRegister;
-            } else {
-                // Swap the operands.
-                RegisterID tmp = op1;
-                op1 = op2;
-                op2 = tmp;
-            }
-        }
-        m_assembler.muls(dest, op1, op2);
-    }
-
-    void mul32(RegisterID src, RegisterID dest)
-    {
-        mul32(src, dest, dest);
-    }
-
-    void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
-    {
-        move(imm, addressTempRegister);
-        m_assembler.muls(dest, src, addressTempRegister);
-    }
-
-    void neg32(RegisterID srcDest)
-    {
-        m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0));
-    }
-
-    void neg32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.rsbs(dest, src, ARMAssembler::getOp2Byte(0));
-    }
-
-    void or32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.orrs(dest, dest, src);
-    }
-
-    void or32(RegisterID src, AbsoluteAddress dest)
-    {
-        move(TrustedImmPtr(dest.m_ptr), addressTempRegister);
-        load32(Address(addressTempRegister), dataTempRegister);
-        or32(src, dataTempRegister);
-        store32(dataTempRegister, addressTempRegister);
-    }
-
-    void or32(TrustedImm32 imm, AbsoluteAddress dest)
-    {
-        move(TrustedImmPtr(dest.m_ptr), addressTempRegister);
-        load32(Address(addressTempRegister), dataTempRegister);
-        or32(imm, dataTempRegister); // It uses S0 as temporary register, we need to reload the address.
-        move(TrustedImmPtr(dest.m_ptr), addressTempRegister);
-        store32(dataTempRegister, addressTempRegister);
-    }
-
-    void or32(TrustedImm32 imm, Address address)
-    {
-        load32(address, addressTempRegister);
-        or32(imm, addressTempRegister, addressTempRegister);
-        store32(addressTempRegister, address);
-    }
-
-    void or32(TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT(dest != addressTempRegister);
-        m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
-    {
-        ASSERT(src != addressTempRegister);
-        m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void or32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        m_assembler.orrs(dest, op1, op2);
-    }
-
-    void rshift32(RegisterID shiftAmount, RegisterID dest)
-    {
-        rshift32(dest, shiftAmount, dest);
-    }
-
-    void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
-    {
-        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
-        m_assembler.bitAnd(addressTempRegister, shiftAmount, w);
-
-        m_assembler.movs(dest, m_assembler.asrRegister(src, addressTempRegister));
-    }
-
-    void rshift32(TrustedImm32 imm, RegisterID dest)
-    {
-        rshift32(dest, imm, dest);
-    }
-
-    void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        if (!imm.m_value)
-            move(src, dest);
-        else
-            m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));
-    }
-
-    void urshift32(RegisterID shiftAmount, RegisterID dest)
-    {
-        urshift32(dest, shiftAmount, dest);
-    }
-
-    void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
-    {
-        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
-        m_assembler.bitAnd(addressTempRegister, shiftAmount, w);
-
-        m_assembler.movs(dest, m_assembler.lsrRegister(src, addressTempRegister));
-    }
-
-    void urshift32(TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
-    }
-    
-    void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        if (!imm.m_value)
-            move(src, dest);
-        else
-            m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
-    }
-
-    void sub32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.subs(dest, dest, src);
-    }
-
-    void sub32(RegisterID left, RegisterID right, RegisterID dest)
-    {
-        m_assembler.subs(dest, left, right);
-    }
-
-    void sub32(TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void sub32(TrustedImm32 imm, Address address)
-    {
-        load32(address, dataTempRegister);
-        sub32(imm, dataTempRegister);
-        store32(dataTempRegister, address);
-    }
-
-    void sub32(Address src, RegisterID dest)
-    {
-        load32(src, dataTempRegister);
-        sub32(dataTempRegister, dest);
-    }
-
-    void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void xor32(RegisterID src, RegisterID dest)
-    {
-        m_assembler.eors(dest, dest, src);
-    }
-
-    void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        m_assembler.eors(dest, op1, op2);
-    }
-
-    void xor32(Address src, RegisterID dest)
-    {
-        load32(src, dataTempRegister);
-        xor32(dataTempRegister, dest);
-    }
-
-    void xor32(TrustedImm32 imm, RegisterID dest)
-    {
-        if (imm.m_value == -1)
-            m_assembler.mvns(dest, dest);
-        else
-            m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
-    {
-        if (imm.m_value == -1)
-            m_assembler.mvns(dest, src);
-        else    
-            m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void countLeadingZeros32(RegisterID src, RegisterID dest)
-    {
-#if WTF_ARM_ARCH_AT_LEAST(5)
-        m_assembler.clz(dest, src);
-#else
-        UNUSED_PARAM(src);
-        UNUSED_PARAM(dest);
-        RELEASE_ASSERT_NOT_REACHED();
-#endif
-    }
-
-    void load8(ImplicitAddress address, RegisterID dest)
-    {
-        m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.offset);
-    }
-
-    void load8(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void load8(const void* address, RegisterID dest)
-    {
-        move(TrustedImmPtr(address), addressTempRegister);
-        m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, addressTempRegister, 0);
-    }
-
-    void load8SignedExtendTo32(Address address, RegisterID dest)
-    {
-        m_assembler.dataTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.offset);
-    }
-
-    void load8SignedExtendTo32(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void load16(ImplicitAddress address, RegisterID dest)
-    {
-        m_assembler.dataTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.offset);
-    }
-
-    void load16(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.baseIndexTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void load16SignedExtendTo32(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void load32(ImplicitAddress address, RegisterID dest)
-    {
-        m_assembler.dataTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.offset);
-    }
-
-    void load32(BaseIndex address, RegisterID dest)
-    {
-        m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-#if CPU(ARMV5_OR_LOWER)
-    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest);
-#else
-    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
-    {
-        load32(address, dest);
-    }
-#endif
-
-    void load16Unaligned(BaseIndex address, RegisterID dest)
-    {
-        load16(address, dest);
-    }
-
-    void abortWithReason(AbortReason reason)
-    {
-        move(TrustedImm32(reason), addressTempRegister);
-        breakpoint();
-    }
-
-    void abortWithReason(AbortReason reason, intptr_t misc)
-    {
-        move(TrustedImm32(misc), dataTempRegister);
-        abortWithReason(reason);
-    }
-
-    ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
-    {
-        ConvertibleLoadLabel result(this);
-        ASSERT(address.offset >= 0 && address.offset <= 255);
-        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
-        return result;
-    }
-
-    DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
-    {
-        DataLabel32 dataLabel(this);
-        m_assembler.ldrUniqueImmediate(addressTempRegister, 0);
-        m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, addressTempRegister);
-        return dataLabel;
-    }
-
-    static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
-    {
-        return value >= -4095 && value <= 4095;
-    }
-
-    DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
-    {
-        DataLabelCompact dataLabel(this);
-        ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
-        if (address.offset >= 0)
-            m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
-        else
-            m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
-        return dataLabel;
-    }
-
-    DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
-    {
-        DataLabel32 dataLabel(this);
-        m_assembler.ldrUniqueImmediate(addressTempRegister, 0);
-        m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, addressTempRegister);
-        return dataLabel;
-    }
-
-    void store8(RegisterID src, BaseIndex address)
-    {
-        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint8, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void store8(RegisterID src, ImplicitAddress address)
-    {
-        m_assembler.dtrUp(ARMAssembler::StoreUint8, src, address.base, address.offset);
-    }
-
-    void store8(RegisterID src, const void* address)
-    {
-        move(TrustedImmPtr(address), addressTempRegister);
-        m_assembler.dtrUp(ARMAssembler::StoreUint8, src, addressTempRegister, 0);
-    }
-
-    void store8(TrustedImm32 imm, ImplicitAddress address)
-    {
-        TrustedImm32 imm8(static_cast<int8_t>(imm.m_value));
-        move(imm8, dataTempRegister);
-        store8(dataTempRegister, address);
-    }
-
-    void store8(TrustedImm32 imm, const void* address)
-    {
-        TrustedImm32 imm8(static_cast<int8_t>(imm.m_value));
-        move(TrustedImm32(reinterpret_cast<ARMWord>(address)), addressTempRegister);
-        move(imm8, dataTempRegister);
-        m_assembler.dtrUp(ARMAssembler::StoreUint8, dataTempRegister, addressTempRegister, 0);
-    }
-
-    void store16(RegisterID src, BaseIndex address)
-    {
-        m_assembler.baseIndexTransfer16(ARMAssembler::StoreUint16, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void store16(RegisterID src, ImplicitAddress address)
-    {
-        m_assembler.dataTransfer16(ARMAssembler::StoreUint16, src, address.base, address.offset);
-    }
-
-    void store32(RegisterID src, ImplicitAddress address)
-    {
-        m_assembler.dataTransfer32(ARMAssembler::StoreUint32, src, address.base, address.offset);
-    }
-
-    void store32(RegisterID src, BaseIndex address)
-    {
-        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void store32(TrustedImm32 imm, ImplicitAddress address)
-    {
-        move(imm, dataTempRegister);
-        store32(dataTempRegister, address);
-    }
-
-    void store32(TrustedImm32 imm, BaseIndex address)
-    {
-        move(imm, dataTempRegister);
-        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, dataTempRegister, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void store32(RegisterID src, const void* address)
-    {
-        m_assembler.ldrUniqueImmediate(addressTempRegister, reinterpret_cast<ARMWord>(address));
-        m_assembler.dtrUp(ARMAssembler::StoreUint32, src, addressTempRegister, 0);
-    }
-
-    void store32(TrustedImm32 imm, const void* address)
-    {
-        m_assembler.ldrUniqueImmediate(addressTempRegister, reinterpret_cast<ARMWord>(address));
-        m_assembler.moveImm(imm.m_value, dataTempRegister);
-        m_assembler.dtrUp(ARMAssembler::StoreUint32, dataTempRegister, addressTempRegister, 0);
-    }
-
-    void pop(RegisterID dest)
-    {
-        m_assembler.pop(dest);
-    }
-
-    void popPair(RegisterID dest1, RegisterID dest2)
-    {
-        m_assembler.pop(dest1);
-        m_assembler.pop(dest2);
-    }
-
-    void push(RegisterID src)
-    {
-        m_assembler.push(src);
-    }
-
-    void push(Address address)
-    {
-        load32(address, dataTempRegister);
-        push(dataTempRegister);
-    }
-
-    void push(TrustedImm32 imm)
-    {
-        move(imm, addressTempRegister);
-        push(addressTempRegister);
-    }
-
-    void pushPair(RegisterID src1, RegisterID src2)
-    {
-        m_assembler.push(src2);
-        m_assembler.push(src1);
-    }
-
-    void move(TrustedImm32 imm, RegisterID dest)
-    {
-        m_assembler.moveImm(imm.m_value, dest);
-    }
-
-    void move(RegisterID src, RegisterID dest)
-    {
-        if (src != dest)
-            m_assembler.mov(dest, src);
-    }
-
-    void move(TrustedImmPtr imm, RegisterID dest)
-    {
-        move(TrustedImm32(imm), dest);
-    }
-
-    void swap(RegisterID reg1, RegisterID reg2)
-    {
-        move(reg1, dataTempRegister);
-        move(reg2, reg1);
-        move(dataTempRegister, reg2);
-    }
-
-    void swap(FPRegisterID fr1, FPRegisterID fr2)
-    {
-        moveDouble(fr1, fpTempRegister);
-        moveDouble(fr2, fr1);
-        moveDouble(fpTempRegister, fr2);
-    }
-
-    void signExtend32ToPtr(RegisterID src, RegisterID dest)
-    {
-        if (src != dest)
-            move(src, dest);
-    }
-
-    void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
-    {
-        if (src != dest)
-            move(src, dest);
-    }
-
-    Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
-    {
-        TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right8);
-    }
-
-    Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
-    {
-        TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right8);
-    }
-
-    Jump branch8(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
-    {
-        TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
-        move(TrustedImmPtr(left.m_ptr), dataTempRegister);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, Address(dataTempRegister), dataTempRegister);
-        return branch32(cond, dataTempRegister, right8);
-    }
-
-    Jump branchPtr(RelationalCondition cond, BaseIndex left, RegisterID right)
-    {
-        load32(left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
-    {
-        m_assembler.cmp(left, right);
-        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
-    }
-
-    Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)
-    {
-        internalCompare32(left, right);
-        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
-    }
-
-    Jump branch32(RelationalCondition cond, RegisterID left, Address right)
-    {
-        load32(right, dataTempRegister);
-        return branch32(cond, left, dataTempRegister);
-    }
-
-    Jump branch32(RelationalCondition cond, Address left, RegisterID right)
-    {
-        load32(left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)
-    {
-        load32(left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
-    {
-        load32(left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
-    {
-        load32WithUnalignedHalfWords(left, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, address, dataTempRegister);
-        return branchTest32(cond, dataTempRegister, mask8);
-    }
-
-    Jump branchTest8(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, address, dataTempRegister);
-        return branchTest32(cond, dataTempRegister, mask8);
-    }
-
-    Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
-        move(TrustedImmPtr(address.m_ptr), dataTempRegister);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, Address(dataTempRegister), dataTempRegister);
-        return branchTest32(cond, dataTempRegister, mask8);
-    }
-
-    Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
-    {
-        ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
-        m_assembler.tst(reg, mask);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
-        ARMWord w = m_assembler.getImm(mask.m_value, addressTempRegister, true);
-        if (w & ARMAssembler::Op2InvertedImmediate)
-            m_assembler.bics(addressTempRegister, reg, w & ~ARMAssembler::Op2InvertedImmediate);
-        else
-            m_assembler.tst(reg, w);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        load32(address, dataTempRegister);
-        return branchTest32(cond, dataTempRegister, mask);
-    }
-
-    Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
-    {
-        load32(address, dataTempRegister);
-        return branchTest32(cond, dataTempRegister, mask);
-    }
-
-    Jump jump()
-    {
-        return Jump(m_assembler.jmp());
-    }
-
-    void jump(RegisterID target, PtrTag)
-    {
-        m_assembler.bx(target);
-    }
-
-    void jump(Address address, PtrTag)
-    {
-        load32(address, ARMRegisters::pc);
-    }
-
-    void jump(AbsoluteAddress address, PtrTag)
-    {
-        move(TrustedImmPtr(address.m_ptr), addressTempRegister);
-        load32(Address(addressTempRegister, 0), ARMRegisters::pc);
-    }
-
-    ALWAYS_INLINE void jump(RegisterID target, RegisterID jumpTag) { UNUSED_PARAM(jumpTag), jump(target, NoPtrTag); }
-    ALWAYS_INLINE void jump(Address address, RegisterID jumpTag) { UNUSED_PARAM(jumpTag), jump(address, NoPtrTag); }
-    ALWAYS_INLINE void jump(AbsoluteAddress address, RegisterID jumpTag) { UNUSED_PARAM(jumpTag), jump(address, NoPtrTag); }
-
-    void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
-    {
-        m_assembler.vmov(dest1, dest2, src);
-    }
-
-    void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
-    {
-        m_assembler.vmov(dest, src1, src2);
-    }
-
-    Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
-            || (cond == NonZero) || (cond == PositiveOrZero));
-        add32(src, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
-            || (cond == NonZero) || (cond == PositiveOrZero));
-        add32(op1, op2, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
-            || (cond == NonZero) || (cond == PositiveOrZero));
-        add32(imm, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
-            || (cond == NonZero) || (cond == PositiveOrZero));
-        add32(src, imm, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
-            || (cond == NonZero) || (cond == PositiveOrZero));
-        add32(imm, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchAdd32(ResultCondition cond, Address src, RegisterID dest)
-    {
-        load32(src, addressTempRegister);
-        return branchAdd32(cond, dest, addressTempRegister, dest);
-    }
-    void mull32(RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        if (op2 == dest) {
-            if (op1 == dest) {
-                move(op2, addressTempRegister);
-                op2 = addressTempRegister;
-            } else {
-                // Swap the operands.
-                RegisterID tmp = op1;
-                op1 = op2;
-                op2 = tmp;
-            }
-        }
-        m_assembler.mull(dataTempRegister, dest, op1, op2);
-        m_assembler.cmp(dataTempRegister, m_assembler.asr(dest, 31));
-    }
-
-    Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        if (cond == Overflow) {
-            mull32(src1, src2, dest);
-            cond = NonZero;
-        }
-        else
-            mul32(src1, src2, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
-    {
-        return branchMul32(cond, src, dest, dest);
-    }
-
-    Jump branchMul32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        if (cond == Overflow) {
-            move(imm, addressTempRegister);
-            mull32(addressTempRegister, src, dest);
-            cond = NonZero;
-        }
-        else
-            mul32(imm, src, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        sub32(src, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        sub32(imm, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        sub32(src, imm, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        m_assembler.subs(dest, op1, op2);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
-    {
-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-        neg32(srcDest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
-    {
-        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
-        or32(src, dest);
-        return Jump(m_assembler.jmp(ARMCondition(cond)));
-    }
-
-    PatchableJump patchableJump()
-    {
-        return PatchableJump(m_assembler.jmp(ARMAssembler::AL, 1));
-    }
-
-    PatchableJump patchableBranch8(RelationalCondition cond, Address address, TrustedImm32 imm)
-    {
-        TrustedImm32 imm8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, imm);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, address, dataTempRegister);
-        return patchableBranch32(cond, dataTempRegister, imm8);
-    }
-
-    PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)
-    {
-        internalCompare32(reg, imm);
-        Jump jump(m_assembler.loadBranchTarget(dataTempRegister, ARMCondition(cond), true));
-        m_assembler.bx(dataTempRegister, ARMCondition(cond));
-        return PatchableJump(jump);
-    }
-
-    PatchableJump patchableBranch32(RelationalCondition cond, Address address, TrustedImm32 imm)
-    {
-        internalCompare32(address, imm);
-        Jump jump(m_assembler.loadBranchTarget(dataTempRegister, ARMCondition(cond), false));
-        m_assembler.bx(dataTempRegister, ARMCondition(cond));
-        return PatchableJump(jump);
-    }
-
-    void breakpoint()
-    {
-        m_assembler.bkpt(0);
-    }
-
-    static bool isBreakpoint(void* address) { return ARMAssembler::isBkpt(address); }
-
-    Call nearCall()
-    {
-        m_assembler.loadBranchTarget(dataTempRegister, ARMAssembler::AL, true);
-        return Call(m_assembler.blx(dataTempRegister), Call::LinkableNear);
-    }
-
-    Call nearTailCall()
-    {
-        return Call(m_assembler.jmp(), Call::LinkableNearTail);
-    }
-
-    Call call(RegisterID target, PtrTag)
-    {
-        return Call(m_assembler.blx(target), Call::None);
-    }
-
-    void call(Address address, PtrTag)
-    {
-        call32(address.base, address.offset);
-    }
-
-    void ret()
-    {
-        m_assembler.bx(linkRegister);
-    }
-
-    void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
-    {
-        m_assembler.cmp(left, right);
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
-    }
-
-    void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
-    {
-        m_assembler.cmp(left, m_assembler.getImm(right.m_value, addressTempRegister));
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
-    }
-
-    void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
-    {
-        TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, left, dataTempRegister);
-        compare32(cond, dataTempRegister, right8, dest);
-    }
-
-    void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)
-    {
-        if (mask.m_value == -1)
-            m_assembler.tst(reg, reg);
-        else
-            m_assembler.tst(reg, m_assembler.getImm(mask.m_value, addressTempRegister));
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
-        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
-    }
-
-    void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
-    {
-        load32(address, dataTempRegister);
-        test32(cond, dataTempRegister, mask, dest);
-    }
-
-    void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
-    {
-        TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
-        MacroAssemblerHelpers::load8OnCondition(*this, cond, address, dataTempRegister);
-        test32(cond, dataTempRegister, mask8, dest);
-    }
-
-    void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
-    {
-        m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, addressTempRegister));
-    }
-
-    void add32(TrustedImm32 imm, AbsoluteAddress address)
-    {
-        load32(address.m_ptr, dataTempRegister);
-        add32(imm, dataTempRegister);
-        store32(dataTempRegister, address.m_ptr);
-    }
-
-    void add64(TrustedImm32 imm, AbsoluteAddress address)
-    {
-        ARMWord tmp;
-
-        move(TrustedImmPtr(address.m_ptr), dataTempRegister);
-        m_assembler.dtrUp(ARMAssembler::LoadUint32, addressTempRegister, dataTempRegister, 0);
-
-        if ((tmp = ARMAssembler::getOp2(imm.m_value)) != ARMAssembler::InvalidImmediate)
-            m_assembler.adds(addressTempRegister, addressTempRegister, tmp);
-        else if ((tmp = ARMAssembler::getOp2(-imm.m_value)) != ARMAssembler::InvalidImmediate)
-            m_assembler.subs(addressTempRegister, addressTempRegister, tmp);
-        else {
-            m_assembler.adds(addressTempRegister, addressTempRegister, m_assembler.getImm(imm.m_value, dataTempRegister));
-            move(TrustedImmPtr(address.m_ptr), dataTempRegister);
-        }
-        m_assembler.dtrUp(ARMAssembler::StoreUint32, addressTempRegister, dataTempRegister, 0);
-
-        m_assembler.dtrUp(ARMAssembler::LoadUint32, addressTempRegister, dataTempRegister, sizeof(ARMWord));
-        if (imm.m_value >= 0)
-            m_assembler.adc(addressTempRegister, addressTempRegister, ARMAssembler::getOp2Byte(0));
-        else
-            m_assembler.sbc(addressTempRegister, addressTempRegister, ARMAssembler::getOp2Byte(0));
-        m_assembler.dtrUp(ARMAssembler::StoreUint32, addressTempRegister, dataTempRegister, sizeof(ARMWord));
-    }
-
-    void sub32(TrustedImm32 imm, AbsoluteAddress address)
-    {
-        load32(address.m_ptr, dataTempRegister);
-        sub32(imm, dataTempRegister);
-        store32(dataTempRegister, address.m_ptr);
-    }
-
-    void load32(const void* address, RegisterID dest)
-    {
-        m_assembler.ldrUniqueImmediate(addressTempRegister, reinterpret_cast<ARMWord>(address));
-        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, addressTempRegister, 0);
-    }
-
-    Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
-    {
-        load32(left.m_ptr, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
-    {
-        load32(left.m_ptr, dataTempRegister);
-        return branch32(cond, dataTempRegister, right);
-    }
-
-    void relativeTableJump(RegisterID index, int scale)
-    {
-        ASSERT(scale >= 0 && scale <= 31);
-        m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
-
-        // NOP the default prefetching
-        m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0);
-    }
-
-    Call call(PtrTag)
-    {
-        ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
-        m_assembler.loadBranchTarget(dataTempRegister, ARMAssembler::AL, true);
-        return Call(m_assembler.blx(dataTempRegister), Call::Linkable);
-    }
-
-    ALWAYS_INLINE Call call(RegisterID callTag) { return UNUSED_PARAM(callTag), call(NoPtrTag); }
-    ALWAYS_INLINE Call call(RegisterID target, RegisterID callTag) { return UNUSED_PARAM(callTag), call(target, NoPtrTag); }
-    ALWAYS_INLINE void call(Address address, RegisterID callTag) { UNUSED_PARAM(callTag), call(address, NoPtrTag); }
-
-    Call tailRecursiveCall()
-    {
-        return Call::fromTailJump(jump());
-    }
-
-    Call makeTailRecursiveCall(Jump oldJump)
-    {
-        return Call::fromTailJump(oldJump);
-    }
-
-    DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)
-    {
-        DataLabelPtr dataLabel(this);
-        m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
-        return dataLabel;
-    }
-
-    DataLabel32 moveWithPatch(TrustedImm32 initialValue, RegisterID dest)
-    {
-        DataLabel32 dataLabel(this);
-        m_assembler.ldrUniqueImmediate(dest, static_cast<ARMWord>(initialValue.m_value));
-        return dataLabel;
-    }
-
-    Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(nullptr))
-    {
-        ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
-        dataLabel = moveWithPatch(initialRightValue, dataTempRegister);
-        Jump jump = branch32(cond, left, dataTempRegister, true);
-        return jump;
-    }
-
-    Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(nullptr))
-    {
-        load32(left, dataTempRegister);
-        ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
-        dataLabel = moveWithPatch(initialRightValue, addressTempRegister);
-        Jump jump = branch32(cond, addressTempRegister, dataTempRegister, true);
-        return jump;
-    }
-
-    Jump branch32WithPatch(RelationalCondition cond, Address left, DataLabel32& dataLabel, TrustedImm32 initialRightValue = TrustedImm32(0))
-    {
-        load32(left, dataTempRegister);
-        ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
-        dataLabel = moveWithPatch(initialRightValue, addressTempRegister);
-        Jump jump = branch32(cond, addressTempRegister, dataTempRegister, true);
-        return jump;
-    }
-
-    DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address)
-    {
-        DataLabelPtr dataLabel = moveWithPatch(initialValue, dataTempRegister);
-        store32(dataTempRegister, address);
-        return dataLabel;
-    }
-
-    DataLabelPtr storePtrWithPatch(ImplicitAddress address)
-    {
-        return storePtrWithPatch(TrustedImmPtr(nullptr), address);
-    }
-
-    // Floating point operators
-    static bool supportsFloatingPoint()
-    {
-        return s_isVFPPresent;
-    }
-
-    static bool supportsFloatingPointTruncate()
-    {
-        return false;
-    }
-
-    static bool supportsFloatingPointSqrt()
-    {
-        return s_isVFPPresent;
-    }
-    static bool supportsFloatingPointAbs() { return false; }
-    static bool supportsFloatingPointRounding() { return false; }
-
-
-    void loadFloat(ImplicitAddress address, FPRegisterID dest)
-    {
-        m_assembler.dataTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.offset);
-    }
-
-    void loadFloat(BaseIndex address, FPRegisterID dest)
-    {
-        m_assembler.baseIndexTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void loadDouble(ImplicitAddress address, FPRegisterID dest)
-    {
-        m_assembler.dataTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.offset);
-    }
-
-    void loadDouble(BaseIndex address, FPRegisterID dest)
-    {
-        m_assembler.baseIndexTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void loadDouble(TrustedImmPtr address, FPRegisterID dest)
-    {
-        move(TrustedImm32(reinterpret_cast<ARMWord>(address.m_value)), addressTempRegister);
-        m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, addressTempRegister, 0);
-    }
-
-    NO_RETURN_DUE_TO_CRASH void ceilDouble(FPRegisterID, FPRegisterID)
-    {
-        ASSERT(!supportsFloatingPointRounding());
-        CRASH();
-    }
-
-    NO_RETURN_DUE_TO_CRASH void floorDouble(FPRegisterID, FPRegisterID)
-    {
-        ASSERT(!supportsFloatingPointRounding());
-        CRASH();
-    }
-
-    NO_RETURN_DUE_TO_CRASH void roundTowardZeroDouble(FPRegisterID, FPRegisterID)
-    {
-        ASSERT(!supportsFloatingPointRounding());
-        CRASH();
-    }
-
-    void storeFloat(FPRegisterID src, ImplicitAddress address)
-    {
-        m_assembler.dataTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.offset);
-    }
-
-    void storeFloat(FPRegisterID src, BaseIndex address)
-    {
-        m_assembler.baseIndexTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void storeDouble(FPRegisterID src, ImplicitAddress address)
-    {
-        m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.offset);
-    }
-
-    void storeDouble(FPRegisterID src, BaseIndex address)
-    {
-        m_assembler.baseIndexTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
-    }
-
-    void storeDouble(FPRegisterID src, TrustedImmPtr address)
-    {
-        move(TrustedImm32(reinterpret_cast<ARMWord>(address.m_value)), addressTempRegister);
-        m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, addressTempRegister, 0);
-    }
-
-    void moveDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        if (src != dest)
-            m_assembler.vmov_f64(dest, src);
-    }
-
-    void moveZeroToDouble(FPRegisterID reg)
-    {
-        static double zeroConstant = 0.;
-        loadDouble(TrustedImmPtr(&zeroConstant), reg);
-    }
-
-    void addDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vadd_f64(dest, dest, src);
-    }
-
-    void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
-    {
-        m_assembler.vadd_f64(dest, op1, op2);
-    }
-
-    void addDouble(Address src, FPRegisterID dest)
-    {
-        loadDouble(src, fpTempRegister);
-        addDouble(fpTempRegister, dest);
-    }
-
-    void addDouble(AbsoluteAddress address, FPRegisterID dest)
-    {
-        loadDouble(TrustedImmPtr(address.m_ptr), fpTempRegister);
-        addDouble(fpTempRegister, dest);
-    }
-
-    void divDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vdiv_f64(dest, dest, src);
-    }
-
-    void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
-    {
-        m_assembler.vdiv_f64(dest, op1, op2);
-    }
-
-    void divDouble(Address src, FPRegisterID dest)
-    {
-        RELEASE_ASSERT_NOT_REACHED(); // Untested
-        loadDouble(src, fpTempRegister);
-        divDouble(fpTempRegister, dest);
-    }
-
-    void subDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vsub_f64(dest, dest, src);
-    }
-
-    void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
-    {
-        m_assembler.vsub_f64(dest, op1, op2);
-    }
-
-    void subDouble(Address src, FPRegisterID dest)
-    {
-        loadDouble(src, fpTempRegister);
-        subDouble(fpTempRegister, dest);
-    }
-
-    void mulDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vmul_f64(dest, dest, src);
-    }
-
-    void mulDouble(Address src, FPRegisterID dest)
-    {
-        loadDouble(src, fpTempRegister);
-        mulDouble(fpTempRegister, dest);
-    }
-
-    void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
-    {
-        m_assembler.vmul_f64(dest, op1, op2);
-    }
-
-    void sqrtDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vsqrt_f64(dest, src);
-    }
-    
-    void absDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vabs_f64(dest, src);
-    }
-
-    void negateDouble(FPRegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vneg_f64(dest, src);
-    }
-
-    void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
-    {
-        m_assembler.vmov_vfp32(dest << 1, src);
-        m_assembler.vcvt_f64_s32(dest, dest << 1);
-    }
-
-    void convertInt32ToDouble(Address src, FPRegisterID dest)
-    {
-        load32(src, dataTempRegister);
-        convertInt32ToDouble(dataTempRegister, dest);
-    }
-
-    void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
-    {
-        move(TrustedImmPtr(src.m_ptr), dataTempRegister);
-        load32(Address(dataTempRegister), dataTempRegister);
-        convertInt32ToDouble(dataTempRegister, dest);
-    }
-
-    void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
-    {
-        m_assembler.vcvt_f64_f32(dst, src);
-    }
-
-    void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
-    {
-        m_assembler.vcvt_f32_f64(dst, src);
-    }
-
-    Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
-    {
-        m_assembler.vcmp_f64(left, right);
-        m_assembler.vmrs_apsr();
-        if (cond & DoubleConditionBitSpecial)
-            m_assembler.cmp(addressTempRegister, addressTempRegister, ARMAssembler::VS);
-        return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
-    }
-
-    // Truncates 'src' to an integer, and places the resulting 'dest'.
-    // If the result is not representable as a 32 bit value, branch.
-    // May also branch for some values that are representable in 32 bits
-    // (specifically, in this case, INT_MIN).
-    enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
-    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
-    {
-        truncateDoubleToInt32(src, dest);
-
-        m_assembler.add(addressTempRegister, dest, ARMAssembler::getOp2Byte(1));
-        m_assembler.bic(addressTempRegister, addressTempRegister, ARMAssembler::getOp2Byte(1));
-
-        ARMWord w = ARMAssembler::getOp2(0x80000000);
-        ASSERT(w != ARMAssembler::InvalidImmediate);
-        m_assembler.cmp(addressTempRegister, w);
-        return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
-    }
-
-    // Result is undefined if the value is outside of the integer range.
-    void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
-    {
-        m_assembler.vcvt_s32_f64(fpTempRegister << 1, src);
-        m_assembler.vmov_arm32(dest, fpTempRegister << 1);
-    }
-
-    void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
-    {
-        m_assembler.vcvt_u32_f64(fpTempRegister << 1, src);
-        m_assembler.vmov_arm32(dest, fpTempRegister << 1);
-    }
-
-    // Convert 'src' to an integer, and places the resulting 'dest'.
-    // If the result is not representable as a 32 bit value, branch.
-    // May also branch for some values that are representable in 32 bits
-    // (specifically, in this case, 0).
-    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true)
-    {
-        m_assembler.vcvt_s32_f64(fpTempRegister << 1, src);
-        m_assembler.vmov_arm32(dest, fpTempRegister << 1);
-
-        // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
-        m_assembler.vcvt_f64_s32(fpTempRegister, fpTempRegister << 1);
-        failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, fpTempRegister));
-
-        // If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
-        if (negZeroCheck)
-            failureCases.append(branchTest32(Zero, dest));
-    }
-
-    Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
-    {
-        m_assembler.mov(addressTempRegister, ARMAssembler::getOp2Byte(0));
-        convertInt32ToDouble(addressTempRegister, scratch);
-        return branchDouble(DoubleNotEqual, reg, scratch);
-    }
-
-    Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
-    {
-        m_assembler.mov(addressTempRegister, ARMAssembler::getOp2Byte(0));
-        convertInt32ToDouble(addressTempRegister, scratch);
-        return branchDouble(DoubleEqualOrUnordered, reg, scratch);
-    }
-
-    // Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
-    static RelationalCondition invert(RelationalCondition cond)
-    {
-        ASSERT((static_cast<uint32_t>(cond & 0x0fffffff)) == 0 && static_cast<uint32_t>(cond) < static_cast<uint32_t>(ARMAssembler::AL));
-        return static_cast<RelationalCondition>(cond ^ 0x10000000);
-    }
-
-    void nop()
-    {
-        m_assembler.nop();
-    }
-
-    void memoryFence()
-    {
-        m_assembler.dmbSY();
-    }
-
-    void storeFence()
-    {
-        m_assembler.dmbISHST();
-    }
-
-    template<PtrTag resultTag, PtrTag locationTag>
-    static FunctionPtr<resultTag> readCallTarget(CodeLocationCall<locationTag> call)
-    {
-        return FunctionPtr<resultTag>(reinterpret_cast<void(*)()>(ARMAssembler::readCallTarget(call.dataLocation())));
-    }
-
-    template<PtrTag startTag, PtrTag destTag>
-    static void replaceWithJump(CodeLocationLabel<startTag> instructionStart, CodeLocationLabel<destTag> destination)
-    {
-        ARMAssembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
-    }
-    
-    static ptrdiff_t maxJumpReplacementSize()
-    {
-        return ARMAssembler::maxJumpReplacementSize();
-    }
-
-    static ptrdiff_t patchableJumpSize()
-    {
-        return ARMAssembler::patchableJumpSize();
-    }
-
-    static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
-    static bool canJumpReplacePatchableBranch32WithPatch() { return false; }
-
-    template<PtrTag tag>
-    static CodeLocationLabel<tag> startOfPatchableBranch32WithPatchOnAddress(CodeLocationDataLabel32<tag>)
-    {
-        UNREACHABLE_FOR_PLATFORM();
-        return CodeLocationLabel<tag>();
-    }
-
-    template<PtrTag tag>
-    static CodeLocationLabel<tag> startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr<tag>)
-    {
-        UNREACHABLE_FOR_PLATFORM();
-        return CodeLocationLabel<tag>();
-    }
-
-    template<PtrTag tag>
-    static CodeLocationLabel<tag> startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr<tag> label)
-    {
-        return label.labelAtOffset(0);
-    }
-
-    template<PtrTag tag>
-    static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel<tag> instructionStart, RegisterID reg, void* initialValue)
-    {
-        ARMAssembler::revertBranchPtrWithPatch(instructionStart.dataLocation(), reg, reinterpret_cast<uintptr_t>(initialValue) & 0xffff);
-    }
-
-    template<PtrTag tag>
-    static void revertJumpReplacementToPatchableBranch32WithPatch(CodeLocationLabel<tag>, Address, int32_t)
-    {
-        UNREACHABLE_FOR_PLATFORM();
-    }
-
-    template<PtrTag tag>
-    static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel<tag>, Address, void*)
-    {
-        UNREACHABLE_FOR_PLATFORM();
-    }
-
-    template<PtrTag callTag, PtrTag destTag>
-    static void repatchCall(CodeLocationCall<callTag> call, CodeLocationLabel<destTag> destination)
-    {
-        ARMAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
-    }
-
-    template<PtrTag callTag, PtrTag destTag>
-    static void repatchCall(CodeLocationCall<callTag> call, FunctionPtr<destTag> destination)
-    {
-        ARMAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
-    }
-
-protected:
-    ARMAssembler::Condition ARMCondition(RelationalCondition cond)
-    {
-        return static_cast<ARMAssembler::Condition>(cond);
-    }
-
-    ARMAssembler::Condition ARMCondition(ResultCondition cond)
-    {
-        return static_cast<ARMAssembler::Condition>(cond);
-    }
-
-    void ensureSpace(int insnSpace, int constSpace)
-    {
-        m_assembler.ensureSpace(insnSpace, constSpace);
-    }
-
-    int sizeOfConstantPool()
-    {
-        return m_assembler.sizeOfConstantPool();
-    }
-
-    void call32(RegisterID base, int32_t offset)
-    {
-        load32(Address(base, offset), dataTempRegister);
-        m_assembler.blx(dataTempRegister);
-    }
-
-private:
-    friend class LinkBuffer;
-
-    void internalCompare32(RegisterID left, TrustedImm32 right)
-    {
-        ARMWord tmp = (!right.m_value || static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
-        if (tmp != ARMAssembler::InvalidImmediate)
-            m_assembler.cmn(left, tmp);
-        else
-            m_assembler.cmp(left, m_assembler.getImm(right.m_value, addressTempRegister));
-    }
-
-    void internalCompare32(Address left, TrustedImm32 right)
-    {
-        ARMWord tmp = (!right.m_value || static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
-        load32(left, dataTempRegister);
-        if (tmp != ARMAssembler::InvalidImmediate)
-            m_assembler.cmn(dataTempRegister, tmp);
-        else
-            m_assembler.cmp(dataTempRegister, m_assembler.getImm(right.m_value, addressTempRegister));
-    }
-
-    template<PtrTag tag>
-    static void linkCall(void* code, Call call, FunctionPtr<tag> function)
-    {
-        if (call.isFlagSet(Call::Tail))
-            ARMAssembler::linkJump(code, call.m_label, function.executableAddress());
-        else
-            ARMAssembler::linkCall(code, call.m_label, function.executableAddress());
-    }
-
-    static const bool s_isVFPPresent;
-};
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
index 5c94391..143c46d 100644 (file)
 
 #include <elf.h>
 #include <fcntl.h>
+#include <mutex>
 #include <sys/mman.h>
 #include <sys/stat.h>
 #include <sys/syscall.h>
 #include <sys/types.h>
 #include <unistd.h>
+#include <wtf/DataLog.h>
 #include <wtf/MonotonicTime.h>
 #include <wtf/PageBlock.h>
 #include <wtf/ProcessID.h>
index 9c6bab3..8f24e8f 100644 (file)
@@ -29,6 +29,7 @@
 
 #include <stdio.h>
 #include <wtf/Lock.h>
+#include <wtf/text/CString.h>
 
 namespace JSC {
 
index 4ee6eea..7f5191d 100644 (file)
@@ -112,7 +112,7 @@ inline void*& CPUState::pc()
     return *reinterpret_cast<void**>(&spr(X86Registers::eip));
 #elif CPU(ARM64)
     return *reinterpret_cast<void**>(&spr(ARM64Registers::pc));
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     return *reinterpret_cast<void**>(&gpr(ARMRegisters::pc));
 #elif CPU(MIPS)
     return *reinterpret_cast<void**>(&spr(MIPSRegisters::pc));
@@ -127,7 +127,7 @@ inline void*& CPUState::fp()
     return *reinterpret_cast<void**>(&gpr(X86Registers::ebp));
 #elif CPU(ARM64)
     return *reinterpret_cast<void**>(&gpr(ARM64Registers::fp));
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     return *reinterpret_cast<void**>(&gpr(ARMRegisters::fp));
 #elif CPU(MIPS)
     return *reinterpret_cast<void**>(&gpr(MIPSRegisters::fp));
@@ -142,7 +142,7 @@ inline void*& CPUState::sp()
     return *reinterpret_cast<void**>(&gpr(X86Registers::esp));
 #elif CPU(ARM64)
     return *reinterpret_cast<void**>(&gpr(ARM64Registers::sp));
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     return *reinterpret_cast<void**>(&gpr(ARMRegisters::sp));
 #elif CPU(MIPS)
     return *reinterpret_cast<void**>(&gpr(MIPSRegisters::sp));
index 1d77d80..3e75574 100644 (file)
@@ -111,7 +111,7 @@ template<typename T> T nextID(T id) { return static_cast<T>(id + 1); }
 #if ENABLE(MASM_PROBE)
 bool isPC(MacroAssembler::RegisterID id)
 {
-#if CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#if CPU(ARM_THUMB2)
     return id == ARMRegisters::pc;
 #else
     UNUSED_PARAM(id);
@@ -573,7 +573,7 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
 #if CPU(X86) || CPU(X86_64)
     auto flagsSPR = X86Registers::eflags;
     uintptr_t flagsMask = 0xc5;
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     auto flagsSPR = ARMRegisters::apsr;
     uintptr_t flagsMask = 0xf8000000;
 #elif CPU(ARM64)
@@ -753,7 +753,7 @@ void testProbeModifiesStackValues()
 #if CPU(X86) || CPU(X86_64)
     MacroAssembler::SPRegisterID flagsSPR = X86Registers::eflags;
     uintptr_t flagsMask = 0xc5;
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     MacroAssembler::SPRegisterID flagsSPR = ARMRegisters::apsr;
     uintptr_t flagsMask = 0xf8000000;
 #elif CPU(ARM64)
index 8d0846a..9c99dad 100644 (file)
@@ -49,12 +49,8 @@ public:
         return 27;
 #elif CPU(ARM64)
         return 40;
-#elif CPU(ARM)
-#if CPU(ARM_THUMB2)
+#elif CPU(ARM_THUMB2)
         return 48;
-#else
-        return 52;
-#endif
 #elif CPU(MIPS)
         return 72;
 #else
@@ -71,12 +67,8 @@ public:
         return 27;
 #elif CPU(ARM64)
         return 40;
-#elif CPU(ARM)
-#if CPU(ARM_THUMB2)
-        return 48;
-#else
+#elif CPU(ARM_THUMB2)
         return 48;
-#endif
 #elif CPU(MIPS)
         return 72;
 #else
@@ -96,12 +88,8 @@ public:
         size_t size = 27;
 #elif CPU(ARM64)
         size_t size = 32;
-#elif CPU(ARM)
-#if CPU(ARM_THUMB2)
+#elif CPU(ARM_THUMB2)
         size_t size = 30;
-#else
-        size_t size = 32;
-#endif
 #elif CPU(MIPS)
         size_t size = 56;
 #else
index f3753d3..d5e47c1 100644 (file)
@@ -983,7 +983,7 @@ public:
         return appendCallWithCallFrameRollbackOnExceptionSetResult(operation, result);
     }
     
-#if !defined(NDEBUG) && !CPU(ARM) && !CPU(MIPS)
+#if !defined(NDEBUG) && !CPU(ARM_THUMB2) && !CPU(MIPS)
     void prepareForExternalCall()
     {
         // We're about to call out to a "native" helper function. The helper
@@ -1059,7 +1059,7 @@ public:
         }
         return call;
     }
-#elif CPU(ARM) && !CPU(ARM_HARDFP)
+#elif CPU(ARM_THUMB2) && !CPU(ARM_HARDFP)
     JITCompiler::Call appendCallSetResult(const FunctionPtr<CFunctionPtrTag> function, FPRReg result)
     {
         JITCompiler::Call call = appendCall(function);
@@ -1067,7 +1067,7 @@ public:
             m_jit.assembler().vmov(result, GPRInfo::returnValueGPR, GPRInfo::returnValueGPR2);
         return call;
     }
-#else // CPU(X86_64) || (CPU(ARM) && CPU(ARM_HARDFP)) || CPU(ARM64) || CPU(MIPS)
+#else // CPU(X86_64) || (CPU(ARM_THUMB2) && CPU(ARM_HARDFP)) || CPU(ARM64) || CPU(MIPS)
     JITCompiler::Call appendCallSetResult(const FunctionPtr<CFunctionPtrTag> function, FPRReg result)
     {
         JITCompiler::Call call = appendCall(function);
index a6ff227..68dd64c 100644 (file)
@@ -44,9 +44,6 @@ bool tryToDisassemble(const MacroAssemblerCodePtr<DisassemblyPtrTag>& codePtr, s
 #elif CPU(X86_64)
     if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle) != CS_ERR_OK)
         return false;
-#elif CPU(ARM_TRADITIONAL)
-    if (cs_open(CS_ARCH_ARM, CS_MODE_ARM, &handle) != CS_ERR_OK)
-        return false;
 #elif CPU(ARM_THUMB2)
     if (cs_open(CS_ARCH_ARM, CS_MODE_THUMB, &handle) != CS_ERR_OK)
         return false;
index 13cba9c..5f38b4f 100644 (file)
@@ -982,7 +982,7 @@ void AssemblyHelpers::debugCall(VM& vm, V_DebugOperation_EPP function, void* arg
     move(TrustedImmPtr(scratchBuffer->addressOfActiveLength()), GPRInfo::regT0);
     storePtr(TrustedImmPtr(scratchSize), GPRInfo::regT0);
 
-#if CPU(X86_64) || CPU(ARM) || CPU(ARM64) || CPU(MIPS)
+#if CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(MIPS)
     move(TrustedImmPtr(buffer), GPRInfo::argumentGPR2);
     move(TrustedImmPtr(argument), GPRInfo::argumentGPR1);
     move(GPRInfo::callFrameRegister, GPRInfo::argumentGPR0);
index 9a352e1..ec295b9 100644 (file)
@@ -521,7 +521,7 @@ public:
     }
 #endif // CPU(X86_64) || CPU(X86)
 
-#if CPU(ARM) || CPU(ARM64)
+#if CPU(ARM_THUMB2) || CPU(ARM64)
     static size_t prologueStackPointerDelta()
     {
         // Prologue saves the framePointerRegister and linkRegister
index 98a846d..6121018 100644 (file)
@@ -183,7 +183,7 @@ private:
         }
     }
 
-#if CPU(MIPS) || (CPU(ARM) && !CPU(ARM_HARDFP))
+#if CPU(MIPS) || (CPU(ARM_THUMB2) && !CPU(ARM_HARDFP))
     template<unsigned NumCrossSources, unsigned NumberOfRegisters>
     ALWAYS_INLINE void setupStubCrossArgs(std::array<GPRReg, NumberOfRegisters> destinations, std::array<FPRReg, NumberOfRegisters> sources) {
         for (unsigned i = 0; i < NumCrossSources; i++) {
@@ -448,7 +448,7 @@ private:
         setupArgumentsImpl<OperationType>(argSourceRegs.addGPRArg().addPoke(), args...);
     }
 
-#elif CPU(ARM) || CPU(MIPS)
+#elif CPU(ARM_THUMB2) || CPU(MIPS)
 
     template<typename OperationType, unsigned numGPRArgs, unsigned numGPRSources, unsigned numFPRArgs, unsigned numFPRSources, unsigned numCrossSources, unsigned extraGPRArgs, unsigned extraPoke, typename... Args>
     void setupArgumentsImpl(ArgCollection<numGPRArgs, numGPRSources, numFPRArgs, numFPRSources, numCrossSources, extraGPRArgs, extraPoke> argSourceRegs, FPRReg arg, Args... args)
@@ -466,7 +466,7 @@ private:
             setupArgumentsImpl<OperationType>(updatedArgSourceRegs.addGPRExtraArg().addGPRExtraArg(), args...);
             return;
         }
-#elif CPU(ARM) && CPU(ARM_HARDFP)
+#elif CPU(ARM_THUMB2) && CPU(ARM_HARDFP)
         unsigned numberOfFPArgumentRegisters = FPRInfo::numberOfArgumentRegisters;
         unsigned currentFPArgCount = argSourceRegs.argCount(arg);
 
@@ -477,7 +477,7 @@ private:
         }
 #endif
 
-#if CPU(MIPS) || (CPU(ARM) && !CPU(ARM_HARDFP))
+#if CPU(MIPS) || (CPU(ARM_THUMB2) && !CPU(ARM_HARDFP))
         // On MIPS and ARM-softfp FP arguments can be passed in GP registers.
         unsigned numberOfGPArgumentRegisters = GPRInfo::numberOfArgumentRegisters;
         unsigned currentGPArgCount = argSourceRegs.argCount(GPRInfo::regT0);
@@ -592,7 +592,7 @@ private:
             pokeArgumentsAligned<OperationType>(argSourceRegs, arg.payloadGPR(), arg.tagGPR(), args...);
     }
 
-#endif // CPU(ARM) || CPU(MIPS)
+#endif // CPU(ARM_THUMB2) || CPU(MIPS)
 #endif // USE(JSVALUE64)
 
     template<typename OperationType, unsigned numGPRArgs, unsigned numGPRSources, unsigned numFPRArgs, unsigned numFPRSources, unsigned numCrossSources, unsigned extraGPRArgs, unsigned extraPoke, typename Arg, typename... Args>
@@ -673,7 +673,7 @@ private:
         static_assert(FunctionTraits<OperationType>::cCallArity() == numGPRArgs + numFPRArgs + extraPoke, "Check the CCall arity");
 #endif
         setupStubArgs<numGPRSources, GPRReg>(clampArrayToSize<numGPRSources, GPRReg>(argSourceRegs.gprDestinations), clampArrayToSize<numGPRSources, GPRReg>(argSourceRegs.gprSources));
-#if CPU(MIPS) || (CPU(ARM) && !CPU(ARM_HARDFP))
+#if CPU(MIPS) || (CPU(ARM_THUMB2) && !CPU(ARM_HARDFP))
         setupStubCrossArgs<numCrossSources>(argSourceRegs.crossDestinations, argSourceRegs.crossSources);
 #else
         static_assert(!numCrossSources, "shouldn't be used on this architecture.");
@@ -802,7 +802,7 @@ public:
 
         // We don't need the current frame beyond this point. Masquerade as our
         // caller.
-#if CPU(ARM) || CPU(ARM64)
+#if CPU(ARM_THUMB2) || CPU(ARM64)
         loadPtr(Address(framePointerRegister, CallFrame::returnPCOffset()), linkRegister);
         subPtr(TrustedImm32(2 * sizeof(void*)), newFrameSizeGPR);
 #if USE(POINTER_PROFILING)
index d5983a5..6df81e1 100644 (file)
@@ -383,7 +383,7 @@ void CallFrameShuffler::prepareForTailCall()
     // sp will point to head0 and we will move it up half a slot
     // manually
     m_newFrameOffset = 0;
-#elif CPU(ARM) || CPU(MIPS)
+#elif CPU(ARM_THUMB2) || CPU(MIPS)
     // We load the frame pointer and link register
     // manually. We could ask the algorithm to load them for us,
     // and it would allow us to use the link register as an extra
@@ -445,7 +445,7 @@ void CallFrameShuffler::prepareForTailCall()
         m_newFrameBase);
 
     // We load the link register manually for architectures that have one
-#if CPU(ARM) || CPU(ARM64)
+#if CPU(ARM_THUMB2) || CPU(ARM64)
     m_jit.loadPtr(MacroAssembler::Address(MacroAssembler::framePointerRegister, CallFrame::returnPCOffset()),
         MacroAssembler::linkRegister);
 #if USE(POINTER_PROFILING)
index 95cccfb..a22c40d 100644 (file)
@@ -85,17 +85,6 @@ SYMBOL_STRING(getHostCallReturnValue) ":" "\n"
     "b " LOCAL_REFERENCE(getHostCallReturnValueWithExecState) "\n"
 );
 
-#elif COMPILER(GCC_COMPATIBLE) && CPU(ARM_TRADITIONAL)
-asm (
-".text" "\n"
-".globl " SYMBOL_STRING(getHostCallReturnValue) "\n"
-HIDE_SYMBOL(getHostCallReturnValue) "\n"
-INLINE_ARM_FUNCTION(getHostCallReturnValue)
-SYMBOL_STRING(getHostCallReturnValue) ":" "\n"
-    "sub r0, sp, #8" "\n"
-    "b " LOCAL_REFERENCE(getHostCallReturnValueWithExecState) "\n"
-);
-
 #elif CPU(ARM64)
 asm (
 ".text" "\n"
index 6e7859d..c8876d0 100644 (file)
@@ -68,13 +68,6 @@ public:
 
     bool generateInline(CCallHelpers& jit, MathICGenerationState& state, bool shouldEmitProfiling = true)
     {
-#if CPU(ARM_TRADITIONAL)
-        // FIXME: Remove this workaround once the proper fixes are landed.
-        // [ARM] Disable Inline Caching on ARMv7 traditional until proper fix
-        // https://bugs.webkit.org/show_bug.cgi?id=159759
-        return false;
-#endif
-
         state.fastPathStart = jit.label();
         size_t startSize = jit.m_assembler.buffer().codeSize();
 
index 5bad3ef..7c94804 100644 (file)
@@ -51,7 +51,7 @@ RegisterSet RegisterSet::reservedHardwareRegisters()
 #else
     return RegisterSet(ARM64Registers::lr);
 #endif // PLATFORM(IOS_FAMILY)
-#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
+#elif CPU(ARM_THUMB2)
     return RegisterSet(ARMRegisters::lr, ARMRegisters::pc);
 #else
     return { };
@@ -137,15 +137,6 @@ RegisterSet RegisterSet::calleeSaveRegisters()
 #endif
     result.set(ARMRegisters::r10);
     result.set(ARMRegisters::r11);
-#elif CPU(ARM_TRADITIONAL)
-    result.set(ARMRegisters::r4);
-    result.set(ARMRegisters::r5);
-    result.set(ARMRegisters::r6);
-    result.set(ARMRegisters::r7);
-    result.set(ARMRegisters::r8);
-    result.set(ARMRegisters::r9);
-    result.set(ARMRegisters::r10);
-    result.set(ARMRegisters::r11);
 #elif CPU(ARM64)
     // We don't include LR in the set of callee-save registers even though it technically belongs
     // there. This is because we use this set to describe the set of registers that need to be saved
@@ -239,7 +230,6 @@ RegisterSet RegisterSet::llintBaselineCalleeSaveRegisters()
 #endif
 #elif CPU(ARM_THUMB2)
     result.set(GPRInfo::regCS0);
-#elif CPU(ARM_TRADITIONAL)
 #elif CPU(ARM64)
     result.set(GPRInfo::regCS6);
     result.set(GPRInfo::regCS7);
@@ -276,7 +266,6 @@ RegisterSet RegisterSet::dfgCalleeSaveRegisters()
     result.set(GPRInfo::regCS6);
 #endif
 #elif CPU(ARM_THUMB2)
-#elif CPU(ARM_TRADITIONAL)
 #elif CPU(ARM64)
     ASSERT(GPRInfo::regCS8 == GPRInfo::tagTypeNumberRegister);
     ASSERT(GPRInfo::regCS9 == GPRInfo::tagMaskRegister);
index 6686df0..7311a6d 100644 (file)
@@ -130,14 +130,7 @@ static InlineCacheAction actionForCell(VM& vm, JSCell* cell)
 
 static bool forceICFailure(ExecState*)
 {
-#if CPU(ARM_TRADITIONAL)
-    // FIXME: Remove this workaround once the proper fixes are landed.
-    // [ARM] Disable Inline Caching on ARMv7 traditional until proper fix
-    // https://bugs.webkit.org/show_bug.cgi?id=159759
-    return true;
-#else
     return Options::forceICFailure();
-#endif
 }
 
 ALWAYS_INLINE static void fireWatchpointsAndClearStubIfNeeded(VM& vm, StructureStubInfo& stubInfo, CodeBlock* codeBlock, AccessGenerationResult& result)
index 31ac39c..0777791 100644 (file)
@@ -350,7 +350,7 @@ static MacroAssemblerCodeRef<JITThunkPtrTag> nativeForGenerator(VM* vm, ThunkFun
     jit.xor64(ARM64Registers::x1, ARM64Registers::x2);
     jit.call(ARM64Registers::x2, JSEntryPtrTag);
 
-#elif CPU(ARM) || CPU(MIPS)
+#elif CPU(ARM_THUMB2) || CPU(MIPS)
 #if CPU(MIPS)
     // Allocate stack space for (unused) 16 bytes (8-byte aligned) for 4 arguments.
     jit.subPtr(JSInterfaceJIT::TrustedImm32(16), JSInterfaceJIT::stackPointerRegister);
index 6b9b798..28485a9 100644 (file)
@@ -34,9 +34,7 @@
 #define OFFLINE_ASM_C_LOOP 1
 #define OFFLINE_ASM_X86 0
 #define OFFLINE_ASM_X86_WIN 0
-#define OFFLINE_ASM_ARM 0
 #define OFFLINE_ASM_ARMv7 0
-#define OFFLINE_ASM_ARMv7_TRADITIONAL 0
 #define OFFLINE_ASM_ARM64 0
 #define OFFLINE_ASM_ARM64E 0
 #define OFFLINE_ASM_X86_64 0
 #define OFFLINE_ASM_ARMv7 0
 #endif
 
-#if CPU(ARM_TRADITIONAL)
-#if WTF_ARM_ARCH_AT_LEAST(7)
-#define OFFLINE_ASM_ARMv7_TRADITIONAL 1
-#define OFFLINE_ASM_ARM 0
-#else
-#define OFFLINE_ASM_ARM 1
-#define OFFLINE_ASM_ARMv7_TRADITIONAL 0
-#endif
-#else
-#define OFFLINE_ASM_ARMv7_TRADITIONAL 0
-#define OFFLINE_ASM_ARM 0
-#endif
-
 #if CPU(X86_64) && !COMPILER(MSVC)
 #define OFFLINE_ASM_X86_64 1
 #else
index 65d5e8d..ec2a32e 100644 (file)
 #  They are callee-save registers, and guaranteed to be distinct from all other
 #  registers on all architectures.
 #
-#  - lr is defined on non-X86 architectures (ARM64, ARM64E, ARMv7, ARM,
-#  ARMv7_TRADITIONAL, MIPS and CLOOP) and holds the return PC
+#  - lr is defined on non-X86 architectures (ARM64, ARM64E, ARMv7, MIPS and CLOOP)
+#  and holds the return PC
 #
-#  - pc holds the (native) program counter on 32-bits ARM architectures (ARM,
-#  ARMv7, ARMv7_TRADITIONAL)
+#  - pc holds the (native) program counter on 32-bits ARM architectures (ARMv7)
 #
 #  - t0, t1, t2, t3, t4 and optionally t5 are temporary registers that can get trashed on
 #  calls, and are pairwise distinct registers. t4 holds the JS program counter, so use
@@ -612,7 +611,7 @@ macro checkStackPointerAlignment(tempReg, location)
             # C_LOOP does not need the alignment, and can use a little perf
             # improvement from avoiding useless work.
         else
-            if ARM or ARMv7 or ARMv7_TRADITIONAL
+            if ARMv7
                 # ARM can't do logical ops with the sp as a source
                 move sp, tempReg
                 andp StackAlignmentMask, tempReg
@@ -629,7 +628,7 @@ end
 
 if C_LOOP or ARM64 or ARM64E or X86_64 or X86_64_WIN
     const CalleeSaveRegisterCount = 0
-elsif ARM or ARMv7_TRADITIONAL or ARMv7
+elsif ARMv7
     const CalleeSaveRegisterCount = 7
 elsif MIPS
     const CalleeSaveRegisterCount = 1
@@ -645,8 +644,6 @@ const VMEntryTotalFrameSize = (CalleeRegisterSaveSize + sizeof VMEntryRecord + S
 
 macro pushCalleeSaves()
     if C_LOOP or ARM64 or ARM64E or X86_64 or X86_64_WIN
-    elsif ARM or ARMv7_TRADITIONAL
-        emit "push {r4-r10}"
     elsif ARMv7
         emit "push {r4-r6, r8-r11}"
     elsif MIPS
@@ -667,8 +664,6 @@ end
 
 macro popCalleeSaves()
     if C_LOOP or ARM64 or ARM64E or X86_64 or X86_64_WIN
-    elsif ARM or ARMv7_TRADITIONAL
-        emit "pop {r4-r10}"
     elsif ARMv7
         emit "pop {r4-r6, r8-r11}"
     elsif MIPS
@@ -686,7 +681,7 @@ macro popCalleeSaves()
 end
 
 macro preserveCallerPCAndCFR()
-    if C_LOOP or ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    if C_LOOP or ARMv7 or MIPS
         push lr
         push cfr
     elsif X86 or X86_WIN or X86_64 or X86_64_WIN
@@ -701,7 +696,7 @@ end
 
 macro restoreCallerPCAndCFR()
     move cfr, sp
-    if C_LOOP or ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    if C_LOOP or ARMv7 or MIPS
         pop cfr
         pop lr
     elsif X86 or X86_WIN or X86_64 or X86_64_WIN
@@ -715,7 +710,6 @@ macro preserveCalleeSavesUsedByLLInt()
     subp CalleeSaveSpaceStackAligned, sp
     if C_LOOP
         storep metadataTable, -PtrSize[cfr]
-    elsif ARM or ARMv7_TRADITIONAL
     elsif ARMv7
         storep metadataTable, -4[cfr]
     elsif ARM64 or ARM64E
@@ -740,7 +734,6 @@ end
 macro restoreCalleeSavesUsedByLLInt()
     if C_LOOP
         loadp -PtrSize[cfr], metadataTable
-    elsif ARM or ARMv7_TRADITIONAL
     elsif ARMv7
         loadp -4[cfr], metadataTable
     elsif ARM64 or ARM64E
@@ -851,7 +844,7 @@ macro restoreCalleeSavesFromVMEntryFrameCalleeSavesBuffer(vm, temp)
 end
 
 macro preserveReturnAddressAfterCall(destinationRegister)
-    if C_LOOP or ARM or ARMv7 or ARMv7_TRADITIONAL or ARM64 or ARM64E or MIPS
+    if C_LOOP or ARMv7 or ARM64 or ARM64E or MIPS
         # In C_LOOP case, we're only preserving the bytecode vPC.
         move lr, destinationRegister
     elsif X86 or X86_WIN or X86_64 or X86_64_WIN
@@ -874,7 +867,7 @@ macro functionPrologue()
         push cfr
     elsif ARM64 or ARM64E
         push cfr, lr
-    elsif C_LOOP or ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    elsif C_LOOP or ARMv7 or MIPS
         push lr
         push cfr
     end
@@ -886,7 +879,7 @@ macro functionEpilogue()
         pop cfr
     elsif ARM64 or ARM64E
         pop lr, cfr
-    elsif C_LOOP or ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    elsif C_LOOP or ARMv7 or MIPS
         pop cfr
         pop lr
     end
@@ -958,7 +951,7 @@ macro prepareForTailCall(callee, temp1, temp2, temp3, callPtrTag)
     addi StackAlignment - 1 + CallFrameHeaderSize, temp2
     andi ~StackAlignmentMask, temp2
 
-    if ARM or ARMv7_TRADITIONAL or ARMv7 or ARM64 or ARM64E or C_LOOP or MIPS
+    if ARMv7 or ARM64 or ARM64E or C_LOOP or MIPS
         addp CallerFrameAndPCSize, sp
         subi CallerFrameAndPCSize, temp2
         loadp CallerFrameAndPC::returnPC[cfr], lr
@@ -1117,7 +1110,7 @@ macro prologue(codeBlockGetter, codeBlockSetter, osrSlowPath, traceSlowPath)
         if ARM64 or ARM64E
             pop lr, cfr
             untagReturnAddress sp
-        elsif ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+        elsif ARMv7 or MIPS
             pop cfr
             pop lr
         else
@@ -1324,10 +1317,6 @@ else
         _relativePCBase:
             move pc, pcBase
             subp 3, pcBase   # Need to back up the PC and set the Thumb2 bit
-        elsif ARM or ARMv7_TRADITIONAL
-        _relativePCBase:
-            move pc, pcBase
-            subp 8, pcBase
         elsif MIPS
             la _relativePCBase, pcBase
             setcallreg pcBase # needed to set $t9 to the right value for the .cpload created by the label.
@@ -1358,7 +1347,7 @@ macro setEntryAddressCommon(index, label, map)
         pcrtoaddr label, t2
         move index, t4
         storep t2, [map, t4, PtrSize]
-    elsif ARM or ARMv7 or ARMv7_TRADITIONAL
+    elsif ARMv7
         mvlbl (label - _relativePCBase), t4
         addp t4, t2, t4
         move index, t3
index 8128a43..7102038 100644 (file)
@@ -88,7 +88,7 @@ macro dispatchAfterCall(size, op, dispatch)
 end
 
 macro cCall2(function)
-    if ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    if ARMv7 or MIPS
         call function
     elsif X86 or X86_WIN
         subp 8, sp
@@ -112,7 +112,7 @@ macro cCall2Void(function)
 end
 
 macro cCall4(function)
-    if ARM or ARMv7 or ARMv7_TRADITIONAL or MIPS
+    if ARMv7 or MIPS
         call function
     elsif X86 or X86_WIN
         push a3
@@ -174,15 +174,11 @@ macro doVMEntry(makeCall)
         addp CallFrameAlignSlots * SlotSize, sp, t3
         andp ~StackAlignmentMask, t3
         subp t3, CallFrameAlignSlots * SlotSize, sp
-    elsif ARM or ARMv7 or ARMv7_TRADITIONAL
+    elsif ARMv7
         addp CallFrameAlignSlots * SlotSize, sp, t3
         clrbp t3, StackAlignmentMask, t3
-        if ARMv7
-            subp t3, CallFrameAlignSlots * SlotSize, t3
-            move t3, sp
-        else
-            subp t3, CallFrameAlignSlots * SlotSize, sp
-        end
+        subp t3, CallFrameAlignSlots * SlotSize, t3
+        move t3, sp
     end
 
     loadi ProtoCallFrame::paddedArgCount[protoCallFrame], t4
@@ -2035,7 +2031,7 @@ macro nativeCallTrampoline(executableOffsetToFunction)
         andp MarkedBlockMask, t3
         loadp MarkedBlockFooterOffset + MarkedBlock::Footer::m_vm[t3], t3
         addp 8, sp
-    elsif ARM or ARMv7 or ARMv7_TRADITIONAL or C_LOOP or MIPS
+    elsif ARMv7 or C_LOOP or MIPS
         if MIPS
         # calling convention says to save stack space for 4 first registers in
         # all cases. To match our 16-byte alignment, that means we need to
@@ -2102,7 +2098,7 @@ macro internalFunctionCallTrampoline(offsetOfFunction)
         andp MarkedBlockMask, t3
         loadp MarkedBlockFooterOffset + MarkedBlock::Footer::m_vm[t3], t3
         addp 8, sp
-    elsif ARM or ARMv7 or ARMv7_TRADITIONAL or C_LOOP or MIPS
+    elsif ARMv7 or C_LOOP or MIPS
         subp 8, sp # align stack pointer
         # t1 already contains the Callee.
         andp MarkedBlockMask, t1
index 8244bba..b0c3362 100644 (file)
@@ -59,19 +59,6 @@ def isARMv7
     case $activeBackend
     when "ARMv7"
         true
-    when "ARMv7_TRADITIONAL", "ARM"
-        false
-    else
-        raise "bad value for $activeBackend: #{$activeBackend}"
-    end
-end
-
-def isARMv7Traditional
-    case $activeBackend
-    when "ARMv7_TRADITIONAL"
-        true
-    when "ARMv7", "ARM"
-        false
     else
         raise "bad value for $activeBackend: #{$activeBackend}"
     end
@@ -104,7 +91,7 @@ def armMoveImmediate(value, register)
         $asm.puts "mov #{register.armOperand}, \##{value}"
     elsif (~value) >= 0 && (~value) < 256
         $asm.puts "mvn #{register.armOperand}, \##{~value}"
-    elsif isARMv7 or isARMv7Traditional
+    elsif isARMv7
         $asm.puts "movw #{register.armOperand}, \##{value & 0xffff}"
         if (value & 0xffff0000) != 0
             $asm.puts "movt #{register.armOperand}, \##{(value >> 16) & 0xffff}"
@@ -301,21 +288,11 @@ def armLowerLabelReferences(list)
 end
 
 class Sequence
-    def getModifiedListARM
-        raise unless $activeBackend == "ARM"
-        getModifiedListARMCommon
-    end
-
     def getModifiedListARMv7
         raise unless $activeBackend == "ARMv7"
         getModifiedListARMCommon
     end
 
-    def getModifiedListARMv7_TRADITIONAL
-        raise unless $activeBackend == "ARMv7_TRADITIONAL"
-        getModifiedListARMCommon
-    end
-
     def getModifiedListARMCommon
         result = @list
         result = riscLowerSimpleBranchOps(result)
@@ -414,21 +391,11 @@ def emitArmTestSet(operands, code)
 end
 
 class Instruction
-    def lowerARM
-        raise unless $activeBackend == "ARM"
-        lowerARMCommon
-    end
-
     def lowerARMv7
         raise unless $activeBackend == "ARMv7"
         lowerARMCommon
     end
 
-    def lowerARMv7_TRADITIONAL
-        raise unless $activeBackend == "ARMv7_TRADITIONAL"
-        lowerARMCommon
-    end
-
     def lowerARMCommon
         case opcode
         when "addi", "addp", "addis", "addps"
index ff065d5..c6cc5ac 100644 (file)
@@ -40,9 +40,7 @@ BACKENDS =
      "X86_WIN",
      "X86_64",
      "X86_64_WIN",
-     "ARM",
      "ARMv7",
-     "ARMv7_TRADITIONAL",
      "ARM64",
      "ARM64E",
      "MIPS",
@@ -60,9 +58,7 @@ WORKING_BACKENDS =
      "X86_WIN",
      "X86_64",
      "X86_64_WIN",
-     "ARM",
      "ARMv7",
-     "ARMv7_TRADITIONAL",
      "ARM64",
      "ARM64E",
      "MIPS",
index 47dfb96..f477587 100644 (file)
@@ -43,7 +43,7 @@ namespace JSC { namespace Yarr {
 template<YarrJITCompileMode compileMode>
 class YarrGenerator : public YarrJITInfo, private MacroAssembler {
 
-#if CPU(ARM)
+#if CPU(ARM_THUMB2)
     static const RegisterID input = ARMRegisters::r0;
     static const RegisterID index = ARMRegisters::r1;
     static const RegisterID length = ARMRegisters::r2;
@@ -3723,7 +3723,7 @@ class YarrGenerator : public YarrJITInfo, private MacroAssembler {
         // The ABI doesn't guarantee the upper bits are zero on unsigned arguments, so clear them ourselves.
         zeroExtend32ToPtr(index, index);
         zeroExtend32ToPtr(length, length);
-#elif CPU(ARM)
+#elif CPU(ARM_THUMB2)
         push(ARMRegisters::r4);
         push(ARMRegisters::r5);
         push(ARMRegisters::r6);
@@ -3776,7 +3776,7 @@ class YarrGenerator : public YarrJITInfo, private MacroAssembler {
 #elif CPU(ARM64)
         if (m_decodeSurrogatePairs)
             popPair(framePointerRegister, linkRegister);
-#elif CPU(ARM)
+#elif CPU(ARM_THUMB2)
         pop(ARMRegisters::r8);
         pop(ARMRegisters::r6);
         pop(ARMRegisters::r5);
index b68d0a6..07c4155 100644 (file)
@@ -1,3 +1,13 @@
+2018-11-21  Yusuke Suzuki  <yusukesuzuki@slowstart.org>
+
+        [JSC] Drop ARM_TRADITIONAL support in LLInt, baseline JIT, and DFG
+        https://bugs.webkit.org/show_bug.cgi?id=191675
+
+        Reviewed by Mark Lam.
+
+        * wtf/InlineASM.h:
+        * wtf/Platform.h:
+
 2018-11-21  Andy Estes  <aestes@apple.com>
 
         [Cocoa] Create a soft-linking file for PassKit
index 33c1a2b..8379a69 100644 (file)
@@ -93,7 +93,7 @@
 #define LOCAL_LABEL_STRING(name) ".L" #name
 #endif
 
-#if (CPU(ARM_TRADITIONAL) && (defined(thumb2) || defined(__thumb2__) || defined(__thumb) || defined(__thumb__))) || CPU(ARM_THUMB2)
+#if CPU(ARM_THUMB2)
 #define INLINE_ARM_FUNCTION(name) ".thumb" "\n" ".thumb_func " THUMB_FUNC_PARAM(name) "\n"
 #else
 #define INLINE_ARM_FUNCTION(name)
index b23a6e9..353f486 100644 (file)
 #if (CPU(ARM_THUMB2) || CPU(ARM64)) && (PLATFORM(IOS_FAMILY) || OS(LINUX) || OS(FREEBSD))
 #define ENABLE_DFG_JIT 1
 #endif
-/* Enable the DFG JIT on ARM. */
-#if CPU(ARM_TRADITIONAL)
-#define ENABLE_DFG_JIT 1
-#endif
 /* Enable the DFG JIT on MIPS. */
 #if CPU(MIPS)
 #define ENABLE_DFG_JIT 1
 #define ENABLE_FAST_TLS_JIT 1
 #endif
 
-#if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(ARM_TRADITIONAL) || CPU(MIPS)
+#if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(MIPS)
 #define ENABLE_MASM_PROBE 1
 #else
 #define ENABLE_MASM_PROBE 0