[X86] Emit BT instruction for single-bit tests.
authorakling@apple.com <akling@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Wed, 7 May 2014 23:22:07 +0000 (23:22 +0000)
committerakling@apple.com <akling@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Wed, 7 May 2014 23:22:07 +0000 (23:22 +0000)
<https://webkit.org/b/132650>

Implement test-bit-and-branch slightly more efficiently by using
BT + JC/JNC instead of TEST + JZ/JNZ when we're only testing for
a single bit.

Reviewed by Michael Saboff.

* assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::singleBitIndex):
(JSC::MacroAssemblerX86Common::branchTest32):
* assembler/X86Assembler.h:
(JSC::X86Assembler::bt_i8r):
(JSC::X86Assembler::bt_i8m):

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@168451 268f45cc-cd09-0410-ab3c-d52691b4dbfc

Source/JavaScriptCore/ChangeLog
Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h
Source/JavaScriptCore/assembler/X86Assembler.h

index f2f92bb..176f6ba 100644 (file)
@@ -1,3 +1,21 @@
+2014-05-07  Andreas Kling  <akling@apple.com>
+
+        [X86] Emit BT instruction for single-bit tests.
+        <https://webkit.org/b/132650>
+
+        Implement test-bit-and-branch slightly more efficiently by using
+        BT + JC/JNC instead of TEST + JZ/JNZ when we're only testing for
+        a single bit.
+
+        Reviewed by Michael Saboff.
+
+        * assembler/MacroAssemblerX86Common.h:
+        (JSC::MacroAssemblerX86Common::singleBitIndex):
+        (JSC::MacroAssemblerX86Common::branchTest32):
+        * assembler/X86Assembler.h:
+        (JSC::X86Assembler::bt_i8r):
+        (JSC::X86Assembler::bt_i8m):
+
 2014-05-07  Mark Lam  <mark.lam@apple.com>
 
         REGRESSION(r166678): Dromaeo/cssquery-dojo.html crashes regularly.
index 6fdf798..f1ec1b0 100644 (file)
@@ -1163,14 +1163,65 @@ public:
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
+    int singleBitIndex(unsigned mask)
+    {
+        switch (mask) {
+        case 0x00000001: return 0;
+        case 0x00000002: return 1;
+        case 0x00000004: return 2;
+        case 0x00000008: return 3;
+        case 0x00000010: return 4;
+        case 0x00000020: return 5;
+        case 0x00000040: return 6;
+        case 0x00000080: return 7;
+        case 0x00000100: return 8;
+        case 0x00000200: return 9;
+        case 0x00000400: return 10;
+        case 0x00000800: return 11;
+        case 0x00001000: return 12;
+        case 0x00002000: return 13;
+        case 0x00004000: return 14;
+        case 0x00008000: return 15;
+        case 0x00010000: return 16;
+        case 0x00020000: return 17;
+        case 0x00040000: return 18;
+        case 0x00080000: return 19;
+        case 0x00100000: return 20;
+        case 0x00200000: return 21;
+        case 0x00400000: return 22;
+        case 0x00800000: return 23;
+        case 0x01000000: return 24;
+        case 0x02000000: return 25;
+        case 0x04000000: return 26;
+        case 0x08000000: return 27;
+        case 0x10000000: return 28;
+        case 0x20000000: return 29;
+        case 0x40000000: return 30;
+        case 0x80000000: return 31;
+        default: return -1;
+        }
+    }
+
     Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
     {
+        int bitIndex = singleBitIndex(mask.m_value);
+        if ((cond == Zero || cond == NonZero) && bitIndex != -1) {
+            m_assembler.bt_i8r(bitIndex, reg);
+            return Jump(m_assembler.jCC(cond == Zero ? X86Assembler::ConditionNC : X86Assembler::ConditionC));
+        }
+
         test32(cond, reg, mask);
         return branch(cond);
     }
 
     Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
     {
+        int bitIndex = singleBitIndex(mask.m_value);
+        if ((cond == Zero || cond == NonZero) && bitIndex != -1) {
+            m_assembler.bt_i8m(bitIndex, address.offset, address.base);
+            return Jump(m_assembler.jCC(cond == Zero ? X86Assembler::ConditionNC : X86Assembler::ConditionC));
+        }
+
         generateTest32(address, mask);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
index 4a01c72..339861b 100644 (file)
@@ -278,6 +278,7 @@ private:
         OP_SETCC            = 0x90,
         OP2_3BYTE_ESCAPE    = 0xAE,
         OP2_IMUL_GvEv       = 0xAF,
+        OP2_GROUP_BT        = 0xBA,
         OP2_MOVZX_GvEb      = 0xB6,
         OP2_MOVSX_GvEb      = 0xBE,
         OP2_MOVZX_GvEw      = 0xB7,
@@ -336,6 +337,8 @@ private:
         GROUP14_OP_PSLLQ = 6,
         GROUP14_OP_PSRLQ = 2,
 
+        GROUP_BT_OP_BT = 4,
+
         ESCAPE_DD_FSTP_doubleReal = 3,
     } GroupOpcodeID;
     
@@ -1221,6 +1224,18 @@ public:
         m_formatter.immediate8(imm);
     }
 
+    void bt_i8r(int bitIndex, RegisterID src)
+    {
+        m_formatter.twoByteOp(OP2_GROUP_BT, GROUP_BT_OP_BT, src);
+        m_formatter.immediate8(bitIndex);
+    }
+
+    void bt_i8m(int bitIndex, int offset, RegisterID base)
+    {
+        m_formatter.twoByteOp(OP2_GROUP_BT, GROUP_BT_OP_BT, base, offset);
+        m_formatter.immediate8(bitIndex);
+    }
+
     void setCC_r(Condition cond, RegisterID dst)
     {
         m_formatter.twoByteOp8(setccOpcode(cond), (GroupOpcodeID)0, dst);