It should be possible to look at disassembly
authorfpizlo@apple.com <fpizlo@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Tue, 19 Jun 2012 19:42:55 +0000 (19:42 +0000)
committerfpizlo@apple.com <fpizlo@apple.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Tue, 19 Jun 2012 19:42:55 +0000 (19:42 +0000)
https://bugs.webkit.org/show_bug.cgi?id=89319

Source/JavaScriptCore:

Reviewed by Sam Weinig.

This imports the udis86 disassembler library. The library is placed
behind an abstraction in disassembler/Disassembler.h, so that we can
in the future use other disassemblers (for other platforms) whenever
appropriate. As a first step, the disassembler is being invoked for
DFG verbose dumps.

If we ever want to merge a new version of udis86 in the future, I've
made notes about changes I made to the library in
disassembler/udis86/differences.txt.

* CMakeLists.txt:
* DerivedSources.make:
* GNUmakefile.list.am:
* JavaScriptCore.pri:
* JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCore.vcproj:
* JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCoreCommon.vsprops:
* JavaScriptCore.xcodeproj/project.pbxproj:
* dfg/DFGJITCompiler.cpp:
(JSC::DFG::JITCompiler::compile):
(JSC::DFG::JITCompiler::compileFunction):
* disassembler: Added.
* disassembler/Disassembler.h: Added.
(JSC):
(JSC::tryToDisassemble):
* disassembler/UDis86Disassembler.cpp: Added.
(JSC):
(JSC::tryToDisassemble):
* disassembler/udis86: Added.
* disassembler/udis86/differences.txt: Added.
* disassembler/udis86/itab.py: Added.
(UdItabGenerator):
(UdItabGenerator.__init__):
(UdItabGenerator.toGroupId):
(UdItabGenerator.genLookupTable):
(UdItabGenerator.genLookupTableList):
(UdItabGenerator.genInsnTable):
(genItabH):
(genItabH.UD_ITAB_H):
(genItabC):
(genItab):
(main):
* disassembler/udis86/optable.xml: Added.
* disassembler/udis86/ud_opcode.py: Added.
(UdOpcodeTables):
(UdOpcodeTables.sizeOfTable):
(UdOpcodeTables.nameOfTable):
(UdOpcodeTables.updateTable):
(UdOpcodeTables.Insn):
(UdOpcodeTables.Insn.__init__):
(UdOpcodeTables.Insn.__init__.opcode):
(UdOpcodeTables.parse):
(UdOpcodeTables.addInsnDef):
(UdOpcodeTables.print_table):
(UdOpcodeTables.print_tree):
* disassembler/udis86/ud_optable.py: Added.
(UdOptableXmlParser):
(UdOptableXmlParser.parseDef):
(UdOptableXmlParser.parse):
(printFn):
(parse):
(main):
* disassembler/udis86/udis86.c: Added.
(ud_init):
(ud_disassemble):
(ud_set_mode):
(ud_set_vendor):
(ud_set_pc):
(ud):
(ud_insn_asm):
(ud_insn_off):
(ud_insn_hex):
(ud_insn_ptr):
(ud_insn_len):
* disassembler/udis86/udis86.h: Added.
* disassembler/udis86/udis86_decode.c: Added.
(eff_adr_mode):
(ud_lookup_mnemonic):
(decode_prefixes):
(modrm):
(resolve_operand_size):
(resolve_mnemonic):
(decode_a):
(decode_gpr):
(resolve_gpr64):
(resolve_gpr32):
(resolve_reg):
(decode_imm):
(decode_modrm_reg):
(decode_modrm_rm):
(decode_o):
(decode_operand):
(decode_operands):
(clear_insn):
(resolve_mode):
(gen_hex):
(decode_insn):
(decode_3dnow):
(decode_ssepfx):
(decode_ext):
(decode_opcode):
(ud_decode):
* disassembler/udis86/udis86_decode.h: Added.
(ud_itab_entry_operand):
(ud_itab_entry):
(ud_lookup_table_list_entry):
(sse_pfx_idx):
(mode_idx):
(modrm_mod_idx):
(vendor_idx):
(is_group_ptr):
(group_idx):
* disassembler/udis86/udis86_extern.h: Added.
* disassembler/udis86/udis86_input.c: Added.
(inp_buff_hook):
(inp_file_hook):
(ud):
(ud_set_user_opaque_data):
(ud_get_user_opaque_data):
(ud_set_input_buffer):
(ud_set_input_file):
(ud_input_skip):
(ud_input_end):
(ud_inp_next):
(ud_inp_back):
(ud_inp_peek):
(ud_inp_move):
(ud_inp_uint8):
(ud_inp_uint16):
(ud_inp_uint32):
(ud_inp_uint64):
* disassembler/udis86/udis86_input.h: Added.
* disassembler/udis86/udis86_itab_holder.c: Added.
* disassembler/udis86/udis86_syn-att.c: Added.
(opr_cast):
(gen_operand):
(ud_translate_att):
* disassembler/udis86/udis86_syn-intel.c: Added.
(opr_cast):
(gen_operand):
(ud_translate_intel):
* disassembler/udis86/udis86_syn.c: Added.
* disassembler/udis86/udis86_syn.h: Added.
(mkasm):
* disassembler/udis86/udis86_types.h: Added.
(ud_operand):
(ud):
* jit/JITCode.h:
(JITCode):
(JSC::JITCode::tryToDisassemble):

Source/WebCore:

Reviewed by Sam Weinig.

Just fixing EFL's build system now that JSC has a new directory.

* CMakeLists.txt:

Source/WTF:

Reviewed by Sam Weinig.

Made changes to Assertions.h to make it friendly to C code again.

Added ENABLE(DISASSEMBLER) and USE(UDIS86) logic to Platform.h.

* wtf/Assertions.h:
* wtf/Platform.h:

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@120745 268f45cc-cd09-0410-ab3c-d52691b4dbfc

36 files changed:
Source/JavaScriptCore/CMakeLists.txt
Source/JavaScriptCore/ChangeLog
Source/JavaScriptCore/DerivedSources.make
Source/JavaScriptCore/GNUmakefile.am
Source/JavaScriptCore/GNUmakefile.list.am
Source/JavaScriptCore/JavaScriptCore.pri
Source/JavaScriptCore/JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCore.vcproj
Source/JavaScriptCore/JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCoreCommon.vsprops
Source/JavaScriptCore/JavaScriptCore.xcodeproj/project.pbxproj
Source/JavaScriptCore/dfg/DFGJITCompiler.cpp
Source/JavaScriptCore/disassembler/Disassembler.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/differences.txt [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/itab.py [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/optable.xml [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/ud_opcode.py [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/ud_optable.py [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_decode.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_decode.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_extern.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_input.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_input.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_syn.c [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_syn.h [new file with mode: 0644]
Source/JavaScriptCore/disassembler/udis86/udis86_types.h [new file with mode: 0644]
Source/JavaScriptCore/jit/JITCode.h
Source/WTF/ChangeLog
Source/WTF/wtf/Assertions.h
Source/WTF/wtf/Platform.h
Source/WebCore/CMakeLists.txt
Source/WebCore/ChangeLog

index 785fc5f..47e8794 100644 (file)
@@ -7,6 +7,7 @@ SET(JavaScriptCore_INCLUDE_DIRECTORIES
     "${JAVASCRIPTCORE_DIR}/bytecode"
     "${JAVASCRIPTCORE_DIR}/bytecompiler"
     "${JAVASCRIPTCORE_DIR}/dfg"
+    "${JAVASCRIPTCORE_DIR}/disassembler"
     "${JAVASCRIPTCORE_DIR}/heap"
     "${JAVASCRIPTCORE_DIR}/debugger"
     "${JAVASCRIPTCORE_DIR}/interpreter"
index b5d3c2e..bc99dd5 100644 (file)
@@ -1,3 +1,160 @@
+2012-06-17  Filip Pizlo  <fpizlo@apple.com>
+
+        It should be possible to look at disassembly
+        https://bugs.webkit.org/show_bug.cgi?id=89319
+
+        Reviewed by Sam Weinig.
+        
+        This imports the udis86 disassembler library. The library is placed
+        behind an abstraction in disassembler/Disassembler.h, so that we can
+        in the future use other disassemblers (for other platforms) whenever
+        appropriate. As a first step, the disassembler is being invoked for
+        DFG verbose dumps.
+        
+        If we ever want to merge a new version of udis86 in the future, I've
+        made notes about changes I made to the library in
+        disassembler/udis86/differences.txt.
+
+        * CMakeLists.txt:
+        * DerivedSources.make:
+        * GNUmakefile.list.am:
+        * JavaScriptCore.pri:
+        * JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCore.vcproj:
+        * JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCoreCommon.vsprops:
+        * JavaScriptCore.xcodeproj/project.pbxproj:
+        * dfg/DFGJITCompiler.cpp:
+        (JSC::DFG::JITCompiler::compile):
+        (JSC::DFG::JITCompiler::compileFunction):
+        * disassembler: Added.
+        * disassembler/Disassembler.h: Added.
+        (JSC):
+        (JSC::tryToDisassemble):
+        * disassembler/UDis86Disassembler.cpp: Added.
+        (JSC):
+        (JSC::tryToDisassemble):
+        * disassembler/udis86: Added.
+        * disassembler/udis86/differences.txt: Added.
+        * disassembler/udis86/itab.py: Added.
+        (UdItabGenerator):
+        (UdItabGenerator.__init__):
+        (UdItabGenerator.toGroupId):
+        (UdItabGenerator.genLookupTable):
+        (UdItabGenerator.genLookupTableList):
+        (UdItabGenerator.genInsnTable):
+        (genItabH):
+        (genItabH.UD_ITAB_H):
+        (genItabC):
+        (genItab):
+        (main):
+        * disassembler/udis86/optable.xml: Added.
+        * disassembler/udis86/ud_opcode.py: Added.
+        (UdOpcodeTables):
+        (UdOpcodeTables.sizeOfTable):
+        (UdOpcodeTables.nameOfTable):
+        (UdOpcodeTables.updateTable):
+        (UdOpcodeTables.Insn):
+        (UdOpcodeTables.Insn.__init__):
+        (UdOpcodeTables.Insn.__init__.opcode):
+        (UdOpcodeTables.parse):
+        (UdOpcodeTables.addInsnDef):
+        (UdOpcodeTables.print_table):
+        (UdOpcodeTables.print_tree):
+        * disassembler/udis86/ud_optable.py: Added.
+        (UdOptableXmlParser):
+        (UdOptableXmlParser.parseDef):
+        (UdOptableXmlParser.parse):
+        (printFn):
+        (parse):
+        (main):
+        * disassembler/udis86/udis86.c: Added.
+        (ud_init):
+        (ud_disassemble):
+        (ud_set_mode):
+        (ud_set_vendor):
+        (ud_set_pc):
+        (ud):
+        (ud_insn_asm):
+        (ud_insn_off):
+        (ud_insn_hex):
+        (ud_insn_ptr):
+        (ud_insn_len):
+        * disassembler/udis86/udis86.h: Added.
+        * disassembler/udis86/udis86_decode.c: Added.
+        (eff_adr_mode):
+        (ud_lookup_mnemonic):
+        (decode_prefixes):
+        (modrm):
+        (resolve_operand_size):
+        (resolve_mnemonic):
+        (decode_a):
+        (decode_gpr):
+        (resolve_gpr64):
+        (resolve_gpr32):
+        (resolve_reg):
+        (decode_imm):
+        (decode_modrm_reg):
+        (decode_modrm_rm):
+        (decode_o):
+        (decode_operand):
+        (decode_operands):
+        (clear_insn):
+        (resolve_mode):
+        (gen_hex):
+        (decode_insn):
+        (decode_3dnow):
+        (decode_ssepfx):
+        (decode_ext):
+        (decode_opcode):
+        (ud_decode):
+        * disassembler/udis86/udis86_decode.h: Added.
+        (ud_itab_entry_operand):
+        (ud_itab_entry):
+        (ud_lookup_table_list_entry):
+        (sse_pfx_idx):
+        (mode_idx):
+        (modrm_mod_idx):
+        (vendor_idx):
+        (is_group_ptr):
+        (group_idx):
+        * disassembler/udis86/udis86_extern.h: Added.
+        * disassembler/udis86/udis86_input.c: Added.
+        (inp_buff_hook):
+        (inp_file_hook):
+        (ud):
+        (ud_set_user_opaque_data):
+        (ud_get_user_opaque_data):
+        (ud_set_input_buffer):
+        (ud_set_input_file):
+        (ud_input_skip):
+        (ud_input_end):
+        (ud_inp_next):
+        (ud_inp_back):
+        (ud_inp_peek):
+        (ud_inp_move):
+        (ud_inp_uint8):
+        (ud_inp_uint16):
+        (ud_inp_uint32):
+        (ud_inp_uint64):
+        * disassembler/udis86/udis86_input.h: Added.
+        * disassembler/udis86/udis86_itab_holder.c: Added.
+        * disassembler/udis86/udis86_syn-att.c: Added.
+        (opr_cast):
+        (gen_operand):
+        (ud_translate_att):
+        * disassembler/udis86/udis86_syn-intel.c: Added.
+        (opr_cast):
+        (gen_operand):
+        (ud_translate_intel):
+        * disassembler/udis86/udis86_syn.c: Added.
+        * disassembler/udis86/udis86_syn.h: Added.
+        (mkasm):
+        * disassembler/udis86/udis86_types.h: Added.
+        (ud_operand):
+        (ud):
+        * jit/JITCode.h:
+        (JITCode):
+        (JSC::JITCode::tryToDisassemble):
+
 2012-06-19  Mark Hahnenberg  <mhahnenberg@apple.com>
 
         GCActivityCallback and IncrementalSweeper should share code
index fb60d30..b0b637e 100644 (file)
@@ -59,6 +59,7 @@ all : \
     StringConstructor.lut.h \
     StringPrototype.lut.h \
     docs/bytecode.html \
+    udis86_itab.h \
 #
 
 # lookup tables for classes
@@ -79,6 +80,11 @@ RegExpJitTables.h: create_regex_tables
 KeywordLookup.h: KeywordLookupGenerator.py Keywords.table
        python $^ > $@
 
+# udis86 instruction tables
+
+udis86_itab.h: $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml
+       (PYTHONPATH=$(JavaScriptCore)/disassembler/udis86 python $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml || exit 1)
+
 # header detection
 
 ifeq ($(OS),MACOS)
index e203d44..96a23f2 100644 (file)
@@ -51,6 +51,7 @@ javascriptcore_cppflags += \
        -I$(srcdir)/Source/JavaScriptCore/bytecode \
        -I$(srcdir)/Source/JavaScriptCore/bytecompiler \
        -I$(srcdir)/Source/JavaScriptCore/dfg \
+       -I$(srcdir)/Source/JavaScriptCore/disassembler \
        -I$(srcdir)/Source/JavaScriptCore/heap \
        -I$(srcdir)/Source/JavaScriptCore/debugger \
        -I$(srcdir)/Source/JavaScriptCore/ForwardingHeaders \
index c42a5f2..63a6c6f 100644 (file)
@@ -221,6 +221,7 @@ javascriptcore_sources += \
        Source/JavaScriptCore/dfg/DFGVariableAccessData.h \
        Source/JavaScriptCore/dfg/DFGVirtualRegisterAllocationPhase.cpp \
        Source/JavaScriptCore/dfg/DFGVirtualRegisterAllocationPhase.h \
+       Source/JavaScriptCore/disassembler/Disassembler.h \
        Source/JavaScriptCore/heap/CopiedAllocator.h \
        Source/JavaScriptCore/heap/CopiedBlock.h \
        Source/JavaScriptCore/heap/CopiedSpace.cpp \
index 94b663a..380bbaf 100644 (file)
@@ -19,6 +19,7 @@ INCLUDEPATH += \
     $$SOURCE_DIR/heap \
     $$SOURCE_DIR/dfg \
     $$SOURCE_DIR/debugger \
+    $$SOURCE_DIR/disassembler \
     $$SOURCE_DIR/interpreter \
     $$SOURCE_DIR/jit \
     $$SOURCE_DIR/llint \
index 430f28d..d77efcf 100644 (file)
                        </File>
                </Filter>
                <Filter
+                       Name="disassembler"
+                       >
+                       <File
+                               RelativePath="..\..\disassembler\Disassembler.h"
+                               >
+                       </File>
+               </Filter>
+               <Filter
                        Name="interpreter"
                        >
                        <File
index fac0af5..df0724e 100644 (file)
@@ -6,7 +6,7 @@
        >
        <Tool
                Name="VCCLCompilerTool"
-               AdditionalIncludeDirectories="&quot;$(ConfigurationBuildDir)\obj\JavaScriptCore\DerivedSources\&quot;;../../;../../API/;../../parser/;../../bytecompiler/;../../dfg/;../../jit/;../../llint/;../../runtime/;../../tools/;../../bytecode/;../../interpreter/;../../wtf/;../../profiler;../../assembler/;../../debugger/;../../heap/;&quot;$(WebKitLibrariesDir)\include&quot;;&quot;$(WebKitLibrariesDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include&quot;;&quot;$(ConfigurationBuildDir)\include\JavaScriptCore&quot;;&quot;$(ConfigurationBuildDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include\private\JavaScriptCore&quot;;&quot;$(WebKitLibrariesDir)\include\pthreads&quot;"
+               AdditionalIncludeDirectories="&quot;$(ConfigurationBuildDir)\obj\JavaScriptCore\DerivedSources\&quot;;../../;../../API/;../../parser/;../../bytecompiler/;../../dfg/;../../disassembler;../../jit/;../../llint/;../../runtime/;../../tools/;../../bytecode/;../../interpreter/;../../wtf/;../../profiler;../../assembler/;../../debugger/;../../heap/;&quot;$(WebKitLibrariesDir)\include&quot;;&quot;$(WebKitLibrariesDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include&quot;;&quot;$(ConfigurationBuildDir)\include\JavaScriptCore&quot;;&quot;$(ConfigurationBuildDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include\private\JavaScriptCore&quot;;&quot;$(WebKitLibrariesDir)\include\pthreads&quot;"
                PreprocessorDefinitions="__STD_C"
                ForcedIncludeFiles="ICUVersion.h"
        />
index 0295a32..4815b5e 100644 (file)
                0FD82E86141F3FF100179C94 /* SpeculatedType.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0FD82E84141F3FDA00179C94 /* SpeculatedType.cpp */; };
                0FE228ED1436AB2700196C48 /* Options.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FE228EB1436AB2300196C48 /* Options.h */; settings = {ATTRIBUTES = (Private, ); }; };
                0FE228EE1436AB2C00196C48 /* Options.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0FE228EA1436AB2300196C48 /* Options.cpp */; };
+               0FF42731158EBD54004CB9FF /* Disassembler.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4272F158EBD44004CB9FF /* Disassembler.h */; settings = {ATTRIBUTES = (Private, ); }; };
+               0FF42732158EBD58004CB9FF /* UDis86Disassembler.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */; };
+               0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42734158EBD94004CB9FF /* udis86_decode.c */; };
+               0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42735158EBD94004CB9FF /* udis86_decode.h */; };
+               0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42736158EBD94004CB9FF /* udis86_extern.h */; };
+               0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42737158EBD94004CB9FF /* udis86_input.c */; };
+               0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF42738158EBD94004CB9FF /* udis86_input.h */; };
+               0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF42739158EBD94004CB9FF /* udis86_syn-att.c */; };
+               0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */; };
+               0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273B158EBD94004CB9FF /* udis86_syn.c */; };
+               0FF42748158EBE91004CB9FF /* udis86_syn.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273C158EBD94004CB9FF /* udis86_syn.h */; };
+               0FF42749158EBE91004CB9FF /* udis86_types.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273D158EBD94004CB9FF /* udis86_types.h */; };
+               0FF4274A158EBE91004CB9FF /* udis86.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4273E158EBD94004CB9FF /* udis86.c */; };
+               0FF4274B158EBE91004CB9FF /* udis86.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FF4273F158EBD94004CB9FF /* udis86.h */; };
+               0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */ = {isa = PBXBuildFile; fileRef = 0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */; };
                0FF922D414F46B410041A24E /* LLIntOffsetsExtractor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0F4680A114BA7F8200BFE272 /* LLIntOffsetsExtractor.cpp */; };
                0FFFC95714EF90A000C72532 /* DFGCFAPhase.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 0FFFC94B14EF909500C72532 /* DFGCFAPhase.cpp */; };
                0FFFC95814EF90A200C72532 /* DFGCFAPhase.h in Headers */ = {isa = PBXBuildFile; fileRef = 0FFFC94C14EF909500C72532 /* DFGCFAPhase.h */; settings = {ATTRIBUTES = (Private, ); }; };
                0FD82E84141F3FDA00179C94 /* SpeculatedType.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = SpeculatedType.cpp; sourceTree = "<group>"; };
                0FE228EA1436AB2300196C48 /* Options.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Options.cpp; sourceTree = "<group>"; };
                0FE228EB1436AB2300196C48 /* Options.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Options.h; sourceTree = "<group>"; };
+               0FF4272F158EBD44004CB9FF /* Disassembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = Disassembler.h; path = disassembler/Disassembler.h; sourceTree = "<group>"; };
+               0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = UDis86Disassembler.cpp; path = disassembler/UDis86Disassembler.cpp; sourceTree = "<group>"; };
+               0FF42734158EBD94004CB9FF /* udis86_decode.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_decode.c; path = disassembler/udis86/udis86_decode.c; sourceTree = "<group>"; };
+               0FF42735158EBD94004CB9FF /* udis86_decode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_decode.h; path = disassembler/udis86/udis86_decode.h; sourceTree = "<group>"; };
+               0FF42736158EBD94004CB9FF /* udis86_extern.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_extern.h; path = disassembler/udis86/udis86_extern.h; sourceTree = "<group>"; };
+               0FF42737158EBD94004CB9FF /* udis86_input.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_input.c; path = disassembler/udis86/udis86_input.c; sourceTree = "<group>"; };
+               0FF42738158EBD94004CB9FF /* udis86_input.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_input.h; path = disassembler/udis86/udis86_input.h; sourceTree = "<group>"; };
+               0FF42739158EBD94004CB9FF /* udis86_syn-att.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-att.c"; path = "disassembler/udis86/udis86_syn-att.c"; sourceTree = "<group>"; };
+               0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "udis86_syn-intel.c"; path = "disassembler/udis86/udis86_syn-intel.c"; sourceTree = "<group>"; };
+               0FF4273B158EBD94004CB9FF /* udis86_syn.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_syn.c; path = disassembler/udis86/udis86_syn.c; sourceTree = "<group>"; };
+               0FF4273C158EBD94004CB9FF /* udis86_syn.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_syn.h; path = disassembler/udis86/udis86_syn.h; sourceTree = "<group>"; };
+               0FF4273D158EBD94004CB9FF /* udis86_types.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86_types.h; path = disassembler/udis86/udis86_types.h; sourceTree = "<group>"; };
+               0FF4273E158EBD94004CB9FF /* udis86.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86.c; path = disassembler/udis86/udis86.c; sourceTree = "<group>"; };
+               0FF4273F158EBD94004CB9FF /* udis86.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udis86.h; path = disassembler/udis86/udis86.h; sourceTree = "<group>"; };
+               0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86_itab_holder.c; path = disassembler/udis86/udis86_itab_holder.c; sourceTree = "<group>"; };
                0FF922CF14F46B130041A24E /* JSCLLIntOffsetsExtractor */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = JSCLLIntOffsetsExtractor; sourceTree = BUILT_PRODUCTS_DIR; };
                0FFFC94B14EF909500C72532 /* DFGCFAPhase.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = DFGCFAPhase.cpp; path = dfg/DFGCFAPhase.cpp; sourceTree = "<group>"; };
                0FFFC94C14EF909500C72532 /* DFGCFAPhase.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = DFGCFAPhase.h; path = dfg/DFGCFAPhase.h; sourceTree = "<group>"; };
                                969A078F0ED1D3AE00F1F681 /* bytecode */,
                                7E39D81D0EC38EFA003AF11A /* bytecompiler */,
                                1480DB9A0DDC2231003CFDF2 /* debugger */,
+                               0FF4272E158EBCCE004CB9FF /* disassembler */,
                                86EC9DB31328DF44002B2AD7 /* dfg */,
                                142E312A134FF0A600AFADB5 /* heap */,
                                1429D77A0ED20D7300B89619 /* interpreter */,
                        name = llint;
                        sourceTree = "<group>";
                };
+               0FF4272E158EBCCE004CB9FF /* disassembler */ = {
+                       isa = PBXGroup;
+                       children = (
+                               0FF42733158EBD64004CB9FF /* udis86 */,
+                               0FF4272F158EBD44004CB9FF /* Disassembler.h */,
+                               0FF42730158EBD44004CB9FF /* UDis86Disassembler.cpp */,
+                       );
+                       name = disassembler;
+                       sourceTree = "<group>";
+               };
+               0FF42733158EBD64004CB9FF /* udis86 */ = {
+                       isa = PBXGroup;
+                       children = (
+                               0FF42734158EBD94004CB9FF /* udis86_decode.c */,
+                               0FF42735158EBD94004CB9FF /* udis86_decode.h */,
+                               0FF42736158EBD94004CB9FF /* udis86_extern.h */,
+                               0FF42737158EBD94004CB9FF /* udis86_input.c */,
+                               0FF42738158EBD94004CB9FF /* udis86_input.h */,
+                               0FF4274C158EBFE1004CB9FF /* udis86_itab_holder.c */,
+                               0FF42739158EBD94004CB9FF /* udis86_syn-att.c */,
+                               0FF4273A158EBD94004CB9FF /* udis86_syn-intel.c */,
+                               0FF4273B158EBD94004CB9FF /* udis86_syn.c */,
+                               0FF4273C158EBD94004CB9FF /* udis86_syn.h */,
+                               0FF4273D158EBD94004CB9FF /* udis86_types.h */,
+                               0FF4273E158EBD94004CB9FF /* udis86.c */,
+                               0FF4273F158EBD94004CB9FF /* udis86.h */,
+                       );
+                       name = udis86;
+                       sourceTree = "<group>";
+               };
                141211000A48772600480255 /* tests */ = {
                        isa = PBXGroup;
                        children = (
                                0F919D0D157EE0A2004A4E7D /* JSSymbolTableObject.h in Headers */,
                                0F919D11157F332C004A4E7D /* JSSegmentedVariableObject.h in Headers */,
                                0F919D2615853CE3004A4E7D /* Watchpoint.h in Headers */,
+                               0FF42731158EBD54004CB9FF /* Disassembler.h in Headers */,
+                               0FF42741158EBE8D004CB9FF /* udis86_decode.h in Headers */,
+                               0FF42742158EBE91004CB9FF /* udis86_extern.h in Headers */,
+                               0FF42744158EBE91004CB9FF /* udis86_input.h in Headers */,
+                               0FF42748158EBE91004CB9FF /* udis86_syn.h in Headers */,
+                               0FF42749158EBE91004CB9FF /* udis86_types.h in Headers */,
+                               0FF4274B158EBE91004CB9FF /* udis86.h in Headers */,
                        );
                        runOnlyForDeploymentPostprocessing = 0;
                };
                        );
                        runOnlyForDeploymentPostprocessing = 0;
                        shellPath = /bin/sh;
-                       shellScript = "mkdir -p \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore/docs\"\ncd \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore\"\n\n/bin/ln -sfh \"${SRCROOT}\" JavaScriptCore\nexport JavaScriptCore=\"JavaScriptCore\"\nexport BUILT_PRODUCTS_DIR=\"../..\"\n\nmake --no-builtin-rules -f \"JavaScriptCore/DerivedSources.make\" -j `/usr/sbin/sysctl -n hw.ncpu`\n\n/usr/bin/env ruby JavaScriptCore/offlineasm/asm.rb JavaScriptCore/llint/LowLevelInterpreter.asm ${BUILT_PRODUCTS_DIR}/JSCLLIntOffsetsExtractor LLIntAssembly.h\n";
+                       shellScript = "mkdir -p \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore/docs\"\ncd \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore\"\n\n/bin/ln -sfh \"${SRCROOT}\" JavaScriptCore\nexport JavaScriptCore=\"JavaScriptCore\"\nexport BUILT_PRODUCTS_DIR=\"../..\"\n\nmake --no-builtin-rules -f \"JavaScriptCore/DerivedSources.make\" -j `/usr/sbin/sysctl -n hw.ncpu` || exit 1\n\n/usr/bin/env ruby JavaScriptCore/offlineasm/asm.rb JavaScriptCore/llint/LowLevelInterpreter.asm ${BUILT_PRODUCTS_DIR}/JSCLLIntOffsetsExtractor LLIntAssembly.h || exit 1\n";
                };
                9319586B09D9F91A00A56FD4 /* Check For Global Initializers */ = {
                        isa = PBXShellScriptBuildPhase;
                                0F919D10157F3329004A4E7D /* JSSegmentedVariableObject.cpp in Sources */,
                                0F919D2515853CE0004A4E7D /* Watchpoint.cpp in Sources */,
                                0F919D2815856773004A4E7D /* SymbolTable.cpp in Sources */,
+                               0FF42732158EBD58004CB9FF /* UDis86Disassembler.cpp in Sources */,
+                               0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */,
+                               0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */,
+                               0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */,
+                               0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */,
+                               0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */,
+                               0FF4274A158EBE91004CB9FF /* udis86.c in Sources */,
+                               0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */,
                                C2E526BD1590EF000054E48D /* HeapTimer.cpp in Sources */,
                        );
                        runOnlyForDeploymentPostprocessing = 0;
index b8b33f2..20f9142 100644 (file)
@@ -223,6 +223,9 @@ bool JITCompiler::compile(JITCode& entry)
     speculative.linkOSREntries(linkBuffer);
 
     entry = JITCode(linkBuffer.finalizeCode(), JITCode::DFGJIT);
+#if DFG_ENABLE(DEBUG_VERBOSE)
+    entry.tryToDisassemble();
+#endif
     return true;
 }
 
@@ -305,6 +308,9 @@ bool JITCompiler::compileFunction(JITCode& entry, MacroAssemblerCodePtr& entryWi
 
     entryWithArityCheck = linkBuffer.locationOf(arityCheck);
     entry = JITCode(linkBuffer.finalizeCode(), JITCode::DFGJIT);
+#if DFG_ENABLE(DEBUG_VERBOSE)
+    entry.tryToDisassemble();
+#endif
     return true;
 }
 
diff --git a/Source/JavaScriptCore/disassembler/Disassembler.h b/Source/JavaScriptCore/disassembler/Disassembler.h
new file mode 100644 (file)
index 0000000..e49defd
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+#ifndef Disassembler_h
+#define Disassembler_h
+
+#include "MacroAssemblerCodeRef.h"
+#include <wtf/Platform.h>
+#include <wtf/StdLibExtras.h>
+
+namespace JSC {
+
+#if ENABLE(DISASSEMBLER)
+bool tryToDisassemble(MacroAssemblerCodePtr, size_t size, FILE* out);
+#else
+inline bool tryToDisassemble(MacroAssemblerCodePtr, size_t, FILE*)
+{
+    return false;
+}
+#endif
+
+} // namespace JSC
+
+#endif // Disassembler_h
+
diff --git a/Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp b/Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp
new file mode 100644 (file)
index 0000000..26ec23b
--- /dev/null
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+#include "config.h"
+#include "Disassembler.h"
+
+#if USE(UDIS86)
+
+#include "udis86.h"
+
+namespace JSC {
+
+bool tryToDisassemble(MacroAssemblerCodePtr codePtr, size_t size, FILE* out)
+{
+    ud_t disassembler;
+    ud_init(&disassembler);
+    ud_set_input_buffer(&disassembler, static_cast<unsigned char*>(codePtr.executableAddress()), size);
+#if CPU(X86_64)
+    ud_set_mode(&disassembler, 64);
+#else
+    ud_set_mode(&disassembler, 32);
+#endif
+    ud_set_pc(&disassembler, bitwise_cast<uintptr_t>(codePtr.executableAddress()));
+    ud_set_syntax(&disassembler, UD_SYN_ATT);
+    
+    while (ud_disassemble(&disassembler)) {
+        char pcString[20];
+        snprintf(pcString, sizeof(pcString), "0x%lx", static_cast<unsigned long>(disassembler.pc));
+        fprintf(out, "%16s: %s\n", pcString, ud_insn_asm(&disassembler));
+    }
+    
+    return true;
+}
+
+} // namespace JSC
+
+#endif // USE(UDIS86)
+
diff --git a/Source/JavaScriptCore/disassembler/udis86/differences.txt b/Source/JavaScriptCore/disassembler/udis86/differences.txt
new file mode 100644 (file)
index 0000000..3ef51ef
--- /dev/null
@@ -0,0 +1,22 @@
+This documents the differences between the stock version of udis86 and the one found
+here:
+
+- All files not named "udis86" were prefixed with "udis86".
+
+- assert() has been changed to ASSERT()
+
+- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to
+  avoid namespace pollution.
+
+- Removal of KERNEL checks.
+
+- Added #include of udis86_extern.h in udis86_decode.c.
+
+- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used.
+
+- Made udis86_syn.h use WTF_ATTRIBUTE_PRINTF. This required making a bunch of little
+  fixes to make the compiler's format string warnings go away.
+
+- Made the code in udis86_syn.h use vsnprintf() instead of vsprintf().
+
+- Fixed udis86_syn-att.c's jump destination printing to work correctly in 64-bit mode.
diff --git a/Source/JavaScriptCore/disassembler/udis86/itab.py b/Source/JavaScriptCore/disassembler/udis86/itab.py
new file mode 100644 (file)
index 0000000..27fa9b3
--- /dev/null
@@ -0,0 +1,354 @@
+# udis86 - scripts/itab.py
+# 
+# Copyright (c) 2009 Vivek Thampi
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without modification, 
+# are permitted provided that the following conditions are met:
+# 
+#     * Redistributions of source code must retain the above copyright notice, 
+#       this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright notice, 
+#       this list of conditions and the following disclaimer in the documentation 
+#       and/or other materials provided with the distribution.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import sys
+
+sys.path.append( '../scripts' );
+
+import ud_optable
+import ud_opcode
+
+class UdItabGenerator( ud_opcode.UdOpcodeTables ):
+
+    OperandDict = {
+        "Ap"       : [    "OP_A"        , "SZ_P"     ],
+        "E"        : [    "OP_E"        , "SZ_NA"    ],
+        "Eb"       : [    "OP_E"        , "SZ_B"     ],
+        "Ew"       : [    "OP_E"        , "SZ_W"     ],
+        "Ev"       : [    "OP_E"        , "SZ_V"     ],
+        "Ed"       : [    "OP_E"        , "SZ_D"     ],
+        "Eq"       : [    "OP_E"        , "SZ_Q"     ],
+        "Ez"       : [    "OP_E"        , "SZ_Z"     ],
+        "Ex"       : [    "OP_E"        , "SZ_MDQ"   ],
+        "Ep"       : [    "OP_E"        , "SZ_P"     ],
+        "G"        : [    "OP_G"        , "SZ_NA"    ],
+        "Gb"       : [    "OP_G"        , "SZ_B"     ],
+        "Gw"       : [    "OP_G"        , "SZ_W"     ],
+        "Gv"       : [    "OP_G"        , "SZ_V"     ],
+        "Gy"       : [    "OP_G"        , "SZ_MDQ"   ],
+        "Gy"       : [    "OP_G"        , "SZ_MDQ"   ],
+        "Gd"       : [    "OP_G"        , "SZ_D"     ],
+        "Gq"       : [    "OP_G"        , "SZ_Q"     ],
+        "Gx"       : [    "OP_G"        , "SZ_MDQ"   ],
+        "Gz"       : [    "OP_G"        , "SZ_Z"     ],
+        "M"        : [    "OP_M"        , "SZ_NA"    ],
+        "Mb"       : [    "OP_M"        , "SZ_B"     ],
+        "Mw"       : [    "OP_M"        , "SZ_W"     ],
+        "Ms"       : [    "OP_M"        , "SZ_W"     ],
+        "Md"       : [    "OP_M"        , "SZ_D"     ],
+        "Mq"       : [    "OP_M"        , "SZ_Q"     ],
+        "Mt"       : [    "OP_M"        , "SZ_T"     ],
+        "Mo"       : [    "OP_M"        , "SZ_O"     ],
+        "MwRv"     : [    "OP_MR"       , "SZ_WV"    ],
+        "MdRy"     : [    "OP_MR"       , "SZ_DY"    ],
+        "MbRv"     : [    "OP_MR"       , "SZ_BV"    ],
+        "I1"       : [    "OP_I1"       , "SZ_NA"    ],
+        "I3"       : [    "OP_I3"       , "SZ_NA"    ],
+        "Ib"       : [    "OP_I"        , "SZ_B"     ],
+        "Isb"      : [    "OP_I"        , "SZ_SB"    ],
+        "Iw"       : [    "OP_I"        , "SZ_W"     ],
+        "Iv"       : [    "OP_I"        , "SZ_V"     ],
+        "Iz"       : [    "OP_I"        , "SZ_Z"     ],
+        "Jv"       : [    "OP_J"        , "SZ_V"     ],
+        "Jz"       : [    "OP_J"        , "SZ_Z"     ],
+        "Jb"       : [    "OP_J"        , "SZ_B"     ],
+        "R"        : [    "OP_R"        , "SZ_RDQ"   ], 
+        "C"        : [    "OP_C"        , "SZ_NA"    ],
+        "D"        : [    "OP_D"        , "SZ_NA"    ],
+        "S"        : [    "OP_S"        , "SZ_NA"    ],
+        "Ob"       : [    "OP_O"        , "SZ_B"     ],
+        "Ow"       : [    "OP_O"        , "SZ_W"     ],
+        "Ov"       : [    "OP_O"        , "SZ_V"     ],
+        "V"        : [    "OP_V"        , "SZ_O"     ],
+        "W"        : [    "OP_W"        , "SZ_O"     ],
+        "Wsd"      : [    "OP_W"        , "SZ_O"     ],
+        "Wss"      : [    "OP_W"        , "SZ_O"     ],
+        "P"        : [    "OP_P"        , "SZ_Q"     ],
+        "Q"        : [    "OP_Q"        , "SZ_Q"     ],
+        "VR"       : [    "OP_VR"       , "SZ_O"     ],
+        "PR"       : [    "OP_PR"       , "SZ_Q"     ],
+        "AL"       : [    "OP_AL"       , "SZ_NA"    ],
+        "CL"       : [    "OP_CL"       , "SZ_NA"    ],
+        "DL"       : [    "OP_DL"       , "SZ_NA"    ],
+        "BL"       : [    "OP_BL"       , "SZ_NA"    ],
+        "AH"       : [    "OP_AH"       , "SZ_NA"    ],
+        "CH"       : [    "OP_CH"       , "SZ_NA"    ],
+        "DH"       : [    "OP_DH"       , "SZ_NA"    ],
+        "BH"       : [    "OP_BH"       , "SZ_NA"    ],
+        "AX"       : [    "OP_AX"       , "SZ_NA"    ],
+        "CX"       : [    "OP_CX"       , "SZ_NA"    ],
+        "DX"       : [    "OP_DX"       , "SZ_NA"    ],
+        "BX"       : [    "OP_BX"       , "SZ_NA"    ],
+        "SI"       : [    "OP_SI"       , "SZ_NA"    ],
+        "DI"       : [    "OP_DI"       , "SZ_NA"    ],
+        "SP"       : [    "OP_SP"       , "SZ_NA"    ],
+        "BP"       : [    "OP_BP"       , "SZ_NA"    ],
+        "eAX"      : [    "OP_eAX"      , "SZ_NA"    ],
+        "eCX"      : [    "OP_eCX"      , "SZ_NA"    ],
+        "eDX"      : [    "OP_eDX"      , "SZ_NA"    ],
+        "eBX"      : [    "OP_eBX"      , "SZ_NA"    ],
+        "eSI"      : [    "OP_eSI"      , "SZ_NA"    ],
+        "eDI"      : [    "OP_eDI"      , "SZ_NA"    ],
+        "eSP"      : [    "OP_eSP"      , "SZ_NA"    ],
+        "eBP"      : [    "OP_eBP"      , "SZ_NA"    ],
+        "rAX"      : [    "OP_rAX"      , "SZ_NA"    ],
+        "rCX"      : [    "OP_rCX"      , "SZ_NA"    ],
+        "rBX"      : [    "OP_rBX"      , "SZ_NA"    ],
+        "rDX"      : [    "OP_rDX"      , "SZ_NA"    ],
+        "rSI"      : [    "OP_rSI"      , "SZ_NA"    ],
+        "rDI"      : [    "OP_rDI"      , "SZ_NA"    ],
+        "rSP"      : [    "OP_rSP"      , "SZ_NA"    ],
+        "rBP"      : [    "OP_rBP"      , "SZ_NA"    ],
+        "ES"       : [    "OP_ES"       , "SZ_NA"    ],
+        "CS"       : [    "OP_CS"       , "SZ_NA"    ],
+        "DS"       : [    "OP_DS"       , "SZ_NA"    ],
+        "SS"       : [    "OP_SS"       , "SZ_NA"    ],
+        "GS"       : [    "OP_GS"       , "SZ_NA"    ],
+        "FS"       : [    "OP_FS"       , "SZ_NA"    ],
+        "ST0"      : [    "OP_ST0"      , "SZ_NA"    ],
+        "ST1"      : [    "OP_ST1"      , "SZ_NA"    ],
+        "ST2"      : [    "OP_ST2"      , "SZ_NA"    ],
+        "ST3"      : [    "OP_ST3"      , "SZ_NA"    ],
+        "ST4"      : [    "OP_ST4"      , "SZ_NA"    ],
+        "ST5"      : [    "OP_ST5"      , "SZ_NA"    ],
+        "ST6"      : [    "OP_ST6"      , "SZ_NA"    ],
+        "ST7"      : [    "OP_ST7"      , "SZ_NA"    ],
+        "NONE"     : [    "OP_NONE"     , "SZ_NA"    ],
+        "ALr8b"    : [    "OP_ALr8b"    , "SZ_NA"    ],
+        "CLr9b"    : [    "OP_CLr9b"    , "SZ_NA"    ],
+        "DLr10b"   : [    "OP_DLr10b"   , "SZ_NA"    ],
+        "BLr11b"   : [    "OP_BLr11b"   , "SZ_NA"    ],
+        "AHr12b"   : [    "OP_AHr12b"   , "SZ_NA"    ],
+        "CHr13b"   : [    "OP_CHr13b"   , "SZ_NA"    ],
+        "DHr14b"   : [    "OP_DHr14b"   , "SZ_NA"    ],
+        "BHr15b"   : [    "OP_BHr15b"   , "SZ_NA"    ],
+        "rAXr8"    : [    "OP_rAXr8"    , "SZ_NA"    ],
+        "rCXr9"    : [    "OP_rCXr9"    , "SZ_NA"    ],
+        "rDXr10"   : [    "OP_rDXr10"   , "SZ_NA"    ],
+        "rBXr11"   : [    "OP_rBXr11"   , "SZ_NA"    ],
+        "rSPr12"   : [    "OP_rSPr12"   , "SZ_NA"    ],
+        "rBPr13"   : [    "OP_rBPr13"   , "SZ_NA"    ],
+        "rSIr14"   : [    "OP_rSIr14"   , "SZ_NA"    ],
+        "rDIr15"   : [    "OP_rDIr15"   , "SZ_NA"    ],
+        "jWP"      : [    "OP_J"        , "SZ_WP"    ],
+        "jDP"      : [    "OP_J"        , "SZ_DP"    ],
+
+    }
+
+    #
+    # opcode prefix dictionary
+    # 
+    PrefixDict = { 
+        "aso"      : "P_aso",   
+        "oso"      : "P_oso",   
+        "rexw"     : "P_rexw", 
+        "rexb"     : "P_rexb",  
+        "rexx"     : "P_rexx",  
+        "rexr"     : "P_rexr",
+        "seg"      : "P_seg",
+        "inv64"    : "P_inv64", 
+        "def64"    : "P_def64", 
+        "depM"     : "P_depM",
+        "cast1"    : "P_c1",    
+        "cast2"    : "P_c2",    
+        "cast3"    : "P_c3",
+        "cast"     : "P_cast",
+        "sext"     : "P_sext"
+    }
+
+    InvalidEntryIdx = 0 
+    InvalidEntry = { 'type'     : 'invalid', 
+                     'mnemonic' : 'invalid', 
+                     'operands' : '', 
+                     'prefixes' : '',
+                     'meta'     : '' }
+
+    Itab     = []   # instruction table
+    ItabIdx  = 1    # instruction table index
+    GtabIdx  = 0    # group table index
+    GtabMeta = []
+
+    ItabLookup = {}
+
+    MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" )
+    
+    def __init__( self ):
+        # first itab entry (0) is Invalid
+        self.Itab.append( self.InvalidEntry )
+        self.MnemonicsTable.extend( self.MnemonicAliases )
+
+    def toGroupId( self, id ):
+        return 0x8000 | id
+
+    def genLookupTable( self, table, scope = '' ):
+        idxArray = [ ]
+        ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 )
+        self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } )
+
+        for _idx in range( self.sizeOfTable( table[ 'type' ] ) ):
+            idx = "%02x" % _idx 
+
+            e   = self.InvalidEntry
+            i   = self.InvalidEntryIdx
+
+            if idx in table[ 'entries' ].keys():
+                e = table[ 'entries' ][ idx ]
+
+            # leaf node (insn)
+            if e[ 'type' ] == 'insn':
+                ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 )
+                self.Itab.append( e )
+            elif e[ 'type' ] != 'invalid':
+                i = self.genLookupTable( e, 'static' )
+
+            idxArray.append( i )
+
+        name = "ud_itab__%s" % tabIdx
+        self.ItabLookup[ tabIdx ] = name
+
+        self.ItabC.write( "\n" );
+        if len( scope ):
+            self.ItabC.write( scope + ' ' )
+        self.ItabC.write( "const uint16_t %s[] = {\n" % name )
+        for i in range( len( idxArray ) ):
+            if i > 0 and i % 4 == 0: 
+                self.ItabC.write( "\n" )
+            if ( i%4 == 0 ):
+                self.ItabC.write( "  /* %2x */" % i)
+            if idxArray[ i ] >= 0x8000:
+                self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] )))
+            else:
+                self.ItabC.write( "%12d," % ( idxArray[ i ] ))
+        self.ItabC.write( "\n" )
+        self.ItabC.write( "};\n" )
+
+        return self.toGroupId( tabIdx )
+
+    def genLookupTableList( self ):
+        self.ItabC.write( "\n\n"  );
+        self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" )
+        for i in range( len( self.GtabMeta ) ):
+            f0 = self.ItabLookup[ i ] + ","
+            f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + ","
+            f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ]
+            self.ItabC.write( "    /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) )
+        self.ItabC.write( "};" )
+
+    def genInsnTable( self ):
+        self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" );
+        idx = 0
+        for e in self.Itab:
+            opr_c = [ "O_NONE", "O_NONE", "O_NONE" ]
+            pfx_c = []
+            opr   = e[ 'operands' ]
+            for i in range(len(opr)): 
+                if not (opr[i] in self.OperandDict.keys()):
+                    print "error: invalid operand declaration: %s\n" % opr[i]
+                opr_c[i] = "O_" + opr[i]
+            opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2])
+
+            for p in e['prefixes']:
+                if not ( p in self.PrefixDict.keys() ):
+                    print "error: invalid prefix specification: %s \n" % pfx
+                pfx_c.append( self.PrefixDict[p] )
+            if len(e['prefixes']) == 0:
+                pfx_c.append( "P_none" )
+            pfx = "|".join( pfx_c )
+
+            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s },\n" \
+                        % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) )
+            idx += 1
+        self.ItabC.write( "};\n" )
+
+        self.ItabC.write( "\n\n"  );
+        self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" )
+        self.ItabC.write( ",\n    ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) )
+        self.ItabC.write( "\n};\n" )
+
+    def genItabH( self ):
+        self.ItabH = open( "udis86_itab.h", "w" )
+
+        # Generate Table Type Enumeration
+        self.ItabH.write( "#ifndef UD_ITAB_H\n" )
+        self.ItabH.write( "#define UD_ITAB_H\n\n" )
+
+        # table type enumeration
+        self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" )
+        self.ItabH.write( "enum ud_table_type {\n    " )
+        enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ]
+        self.ItabH.write( ",\n    ".join( enum ) )
+        self.ItabH.write( "\n};\n\n" );
+
+        # mnemonic enumeration
+        self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" )
+        enum  = "enum ud_mnemonic_code {\n    "
+        enum += ",\n    ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] )
+        enum += "\n} UD_ATTR_PACKED;\n"
+        self.ItabH.write( enum )
+        self.ItabH.write( "\n" )
+
+        self.ItabH.write("\n/* itab entry operand definitions */\n");
+        operands = self.OperandDict.keys()
+        operands.sort()
+        for o in operands:
+            self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" %
+                    (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1]));
+        self.ItabH.write("\n\n");
+
+        self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" )
+
+        self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" )
+
+        self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" )
+    
+        self.ItabH.close()
+
+
+    def genItabC( self ):
+        self.ItabC = open( "udis86_itab.c", "w" )
+        self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" )
+        self.ItabC.write( " */\n" );
+        self.ItabC.write( "#include \"udis86_decode.h\"\n\n" );
+
+        self.genLookupTable( self.OpcodeTable0 ) 
+        self.genLookupTableList()
+        self.genInsnTable()
+
+        self.ItabC.close()
+
+    def genItab( self ):
+        self.genItabC()
+        self.genItabH()
+
+def main():
+    generator = UdItabGenerator()
+    optableXmlParser = ud_optable.UdOptableXmlParser()
+    optableXmlParser.parse( sys.argv[ 1 ], generator.addInsnDef )
+
+    generator.genItab()
+
+if __name__ == '__main__':
+    main()
diff --git a/Source/JavaScriptCore/disassembler/udis86/optable.xml b/Source/JavaScriptCore/disassembler/udis86/optable.xml
new file mode 100644 (file)
index 0000000..14b4ac5
--- /dev/null
@@ -0,0 +1,8959 @@
+<?xml version="1.0"?>
+<?xml-stylesheet href="optable.xsl" type="text/xsl"?>
+<x86optable>
+
+    <instruction>
+        <mnemonic>aaa</mnemonic>
+        <def>
+            <opc>37</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>aad</mnemonic>
+        <def>
+            <opc>d5</opc>
+            <opr>Ib</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>aam</mnemonic>
+        <def>
+            <opc>d4</opc>
+            <opr>Ib</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>aas</mnemonic>
+        <def>
+            <opc>3f</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>adc</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>10</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>11</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>12</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>13</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>14</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>15</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=2</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=2</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=2</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=2</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>add</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>00</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>01</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>02</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>03</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>04</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>05</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=0</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=0</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=0</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=0</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <!--
+     SSE2
+     -->
+
+    <instruction>
+        <mnemonic>addpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 58</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>addps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 58</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>addsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 58</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>addss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 58</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+     <instruction>
+        <mnemonic>and</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>20</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>21</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>22</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>23</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>24</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>25</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>80 /reg=4</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=4</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=4</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=4</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>andpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 54</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>andps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 54</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>andnpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 55</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>andnps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 55</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>arpl</mnemonic>
+        <def>
+            <pfx>aso</pfx>
+            <opc>63 /m=16</opc>
+            <opr>Ew Gw</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso</pfx>
+            <opc>63 /m=32</opc>
+            <opr>Ew Gw</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsxd</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexx rexr rexb</pfx>
+            <opc>63 /m=64</opc>
+            <opr>Gv Ed</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bound</mnemonic>
+        <def>
+            <pfx>aso oso</pfx>
+            <opc>62</opc>
+            <opr>Gv M</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bsf</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f bc</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bsr</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f bd</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bswap</mnemonic>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f c8</opc>
+            <opr>rAXr8</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f c9</opc>
+            <opr>rCXr9</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f ca</opc>
+            <opr>rDXr10</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f cb</opc>
+            <opr>rBXr11</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f cc</opc>
+            <opr>rSPr12</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f cd</opc>
+            <opr>rBPr13</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f ce</opc>
+            <opr>rSIr14</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>0f cf</opc>
+            <opr>rDIr15</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bt</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ba /reg=4</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f a3</opc>
+            <opr>Ev Gv</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>btc</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f bb</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ba /reg=7</opc>
+            <opr>Ev Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>btr</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b3</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ba /reg=6</opc>
+            <opr>Ev Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>bts</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ab</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ba /reg=5</opc>
+            <opr>Ev Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>call</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=2</opc>
+            <opr>Ev</opr>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=3</opc>
+            <opr>Ep</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>e8</opc>
+            <opr>Jz</opr>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9a</opc>
+            <opr>Ap</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cbw</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>98 /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cwde</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>98 /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cdqe</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>98 /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>clc</mnemonic>
+        <def>
+            <opc>f8</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cld</mnemonic>
+        <def>
+            <opc>fc</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>clflush</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /reg=7 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>clgi</mnemonic>
+        <vendor>amd</vendor>
+        <def>
+            <opc>0f 01 /reg=3 /mod=11 /rm=5</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cli</mnemonic>
+        <def>
+            <opc>fa</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>clts</mnemonic>
+        <def>
+            <opc>0f 06</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmc</mnemonic>
+        <def>
+            <opc>f5</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovo</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 40</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovno</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 41</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovb</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 42</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovae</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 43</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovz</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 44</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovnz</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 45</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovbe</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 46</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmova</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 47</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovs</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 48</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovns</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 49</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovp</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4a</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovnp</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovl</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4c</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovge</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4d</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovle</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4e</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmovg</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 4f</opc>
+            <opr>Gv Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmp</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>38</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>39</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>3a</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>3b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>3c</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>3d</opc>
+            <opr>rAX Iz</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=7</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=7</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=7</opc>
+            <opr>Ev Iz</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=7</opc>
+            <opr>Ev Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmppd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f c2</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f c2</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpsb</mnemonic>
+        <def>
+            <opc>a6</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpsw</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>a7 /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpsd</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>a7 /o=32</opc>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f c2</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpsq</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>a7 /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f c2</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpxchg</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f b0</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b1</opc>
+            <opr>Ev Gv</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpxchg8b</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f c7 /reg=1</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>comisd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>comiss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cpuid</mnemonic>
+        <def>
+            <opc>0f a2</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtdq2pd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f e6</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtdq2ps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5b</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtpd2dq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f e6</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtpd2pi</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2d</opc>
+            <opr>P W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtpd2ps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5a</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtpi2ps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2a</opc>
+            <opr>V Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtpi2pd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2a</opc>
+            <opr>V Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtps2dq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5b</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtps2pi</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2d</opc>
+            <opr>P W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtps2pd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5a</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtsd2si</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef2 0f 2d</opc>
+            <opr>Gy W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtsd2ss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 5a</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtsi2ss</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef3 0f 2a</opc>
+            <opr>V Ex</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtss2si</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef3 0f 2d</opc>
+            <opr>Gy W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtss2sd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5a</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttpd2pi</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2c</opc>
+            <opr>P W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttpd2dq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e6</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttps2dq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5b</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttps2pi</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2c</opc>
+            <opr>P W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttsd2si</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef2 0f 2c</opc>
+            <opr>Gy Wsd</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvtsi2sd</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef2 0f 2a</opc>
+            <opr>V Ex</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cvttss2si</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>ssef3 0f 2c</opc>
+            <opr>Gy Wsd</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cwd</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>99 /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cdq</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>99 /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cqo</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>99 /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>daa</mnemonic>
+        <def>
+            <opc>27</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>das</mnemonic>
+        <def>
+            <opc>2f</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>dec</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>48</opc>
+            <opr>eAX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>49</opc>
+            <opr>eCX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4a</opc>
+            <opr>eDX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4b</opc>
+            <opr>eBX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4c</opc>
+            <opr>eSP</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4d</opc>
+            <opr>eBP</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4e</opc>
+            <opr>eSI</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>4f</opc>
+            <opr>eDI</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>fe /reg=1</opc>
+            <opr>Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=1</opc>
+            <opr>Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>div</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=6</opc>
+            <opr>Ev</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=6</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>divpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>divps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>divsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 5e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>divss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>emms</mnemonic>
+        <def>
+            <opc>0f 77</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>enter</mnemonic>
+        <def>
+            <opc>c8</opc>
+            <opr>Iw Ib</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>f2xm1</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=30</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fabs</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=21</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fadd</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=0</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=0</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=00</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=01</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=02</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=03</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=04</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=05</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=06</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=07</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=00</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=01</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=02</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=03</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=04</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=05</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=06</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=07</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>faddp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=00</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=01</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=02</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=03</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=04</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=05</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=06</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=07</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fbld</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=4</opc>
+            <opr>Mt</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fbstp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=6</opc>
+            <opr>Mt</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fchs</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=20</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fclex</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=22</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovb</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>da /mod=11 /x87=00</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=01</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=02</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=03</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=04</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=05</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=06</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=07</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmove</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>da /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=09</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=0f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovbe</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>da /mod=11 /x87=10</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=11</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=12</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=13</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=14</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=15</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=16</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=17</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovu</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>da /mod=11 /x87=18</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=19</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>da /mod=11 /x87=1f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovnb</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=00</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=01</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=02</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=03</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=04</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=05</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=06</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=07</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovne</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=09</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=0f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovnbe</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=10</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=11</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=12</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=13</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=14</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=15</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=16</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=17</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcmovnu</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=18</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=19</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=1f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fucomi</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=28</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=29</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=2f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcom</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=2</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=2</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=10</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=11</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=12</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=13</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=14</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=15</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=16</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=17</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcom2</mnemonic>
+        <class>X87 UNDOC</class>
+        <def>
+            <opc>dc /mod=11 /x87=10</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=11</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=12</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=13</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=14</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=15</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=16</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=17</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcomp3</mnemonic>
+        <class>X87 UNDOC</class>
+        <def>
+            <opc>dc /mod=11 /x87=18</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=19</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=1f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcomi</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=30</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=31</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=32</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=33</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=34</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=35</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=36</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>db /mod=11 /x87=37</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fucomip</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>df /mod=11 /x87=28</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=29</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=2f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcomip</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>df /mod=11 /x87=30</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=31</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=32</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=33</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=34</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=35</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=36</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=37</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcomp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=3</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=3</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=18</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=19</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=1f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcomp5</mnemonic>
+        <class>X87 UNDOC</class>
+        <def>
+            <opc>de /mod=11 /x87=10</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=11</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=12</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=13</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=14</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=15</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=16</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=17</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcompp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=19</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fcos</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3f</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fdecstp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=36</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fdiv</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=6</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=38</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=39</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=3f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=6</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=30</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=31</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=32</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=33</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=34</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=35</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=36</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=37</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fdivp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=38</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=39</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=3f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fdivr</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=7</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=30</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=31</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=32</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=33</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=34</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=35</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=36</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=37</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=7</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=38</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=39</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=3f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fdivrp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=30</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=31</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=32</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=33</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=34</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=35</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=36</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=37</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>femms</mnemonic>
+        <def>
+            <opc>0f 0e</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ffree</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>dd /mod=11 /x87=00</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=01</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=02</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=03</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=04</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=05</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=06</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=07</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ffreep</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>df /mod=11 /x87=00</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=01</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=02</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=03</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=04</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=05</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=06</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=07</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ficom</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=2</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=2</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ficomp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=3</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=3</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fild</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=0</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=5</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=0</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fncstp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=37</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fninit</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>db /mod=11 /x87=23</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fiadd</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=0</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=0</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fidivr</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=7</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=7</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fidiv</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=6</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=6</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fisub</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=4</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=4</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fisubr</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=5</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=5</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fist</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=2</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=2</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fistp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=3</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=7</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=3</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fisttp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=1</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=1</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>df /mod=!11 /reg=1</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fld</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=5</opc>
+            <opr>Mt</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=0</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=0</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=00</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=01</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=02</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=03</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=04</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=05</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=06</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=07</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fld1</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=28</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldl2t</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=29</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldl2e</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=2a</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldlpi</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=2b</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldlg2</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=2c</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldln2</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=2d</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldz</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=2e</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldcw</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=5</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fldenv</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=4</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fmul</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=1</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=09</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=0f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=1</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=09</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=0f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fmulp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=09</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=0f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fimul</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>da /mod=!11 /reg=1</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>de /mod=!11 /reg=1</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fnop</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=10</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fpatan</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=33</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fprem</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=38</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fprem1</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=35</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fptan</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>frndint</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3c</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>frstor</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=4</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fnsave</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=6</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fscale</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3d</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsin</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3e</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsincos</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3b</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsqrt</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=3a</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fstp</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>db /mod=!11 /reg=7</opc>
+            <opr>Mt</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=3</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=3</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=18</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=19</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=1f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fstp1</mnemonic>
+        <def>
+            <opc>d9 /mod=11 /x87=18</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=19</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=1f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fstp8</mnemonic>
+        <def>
+            <opc>df /mod=11 /x87=10</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=11</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=12</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=13</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=14</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=15</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=16</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=17</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fstp9</mnemonic>
+        <def>
+            <opc>df /mod=11 /x87=18</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=19</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=1f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fst</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=2</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=2</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=10</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=11</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=12</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=13</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=14</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=15</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=16</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=17</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fnstcw</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=7</opc>
+            <opr>Mw</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fnstenv</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d9 /mod=!11 /reg=6</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fnstsw</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dd /mod=!11 /reg=7</opc>
+            <opr>Mw</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=20</opc>
+            <opr>AX</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsub</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=4</opc>
+            <opr>Md</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=4</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=20</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=21</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=22</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=23</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=24</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=25</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=26</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=27</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=28</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=29</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=2f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsubp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=28</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=29</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2a</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2b</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2c</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2d</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2e</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=2f</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsubr</mnemonic>
+        <class>X87</class>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>dc /mod=!11 /reg=5</opc>
+            <opr>Mq</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=28</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=29</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d8 /mod=11 /x87=2f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=20</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=21</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=22</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=23</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=24</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=25</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=26</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>dc /mod=11 /x87=27</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d8 /mod=!11 /reg=5</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fsubrp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>de /mod=11 /x87=20</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=21</opc>
+            <opr>ST1 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=22</opc>
+            <opr>ST2 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=23</opc>
+            <opr>ST3 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=24</opc>
+            <opr>ST4 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=25</opc>
+            <opr>ST5 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=26</opc>
+            <opr>ST6 ST0</opr>
+        </def>
+        <def>
+            <opc>de /mod=11 /x87=27</opc>
+            <opr>ST7 ST0</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ftst</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=24</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fucom</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>dd /mod=11 /x87=20</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=21</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=22</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=23</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=24</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=25</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=26</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=27</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fucomp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>dd /mod=11 /x87=28</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=29</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=2f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fucompp</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>da /mod=11 /x87=29</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxam</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=25</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxch</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=08</opc>
+            <opr>ST0 ST0</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=09</opc>
+            <opr>ST0 ST1</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0a</opc>
+            <opr>ST0 ST2</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0b</opc>
+            <opr>ST0 ST3</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0c</opc>
+            <opr>ST0 ST4</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0d</opc>
+            <opr>ST0 ST5</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0e</opc>
+            <opr>ST0 ST6</opr>
+        </def>
+        <def>
+            <opc>d9 /mod=11 /x87=0f</opc>
+            <opr>ST0 ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxch4</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>dd /mod=11 /x87=08</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=09</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>dd /mod=11 /x87=0f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxch7</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>df /mod=11 /x87=08</opc>
+            <opr>ST0</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=09</opc>
+            <opr>ST1</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0a</opc>
+            <opr>ST2</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0b</opc>
+            <opr>ST3</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0c</opc>
+            <opr>ST4</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0d</opc>
+            <opr>ST5</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0e</opc>
+            <opr>ST6</opr>
+        </def>
+        <def>
+            <opc>df /mod=11 /x87=0f</opc>
+            <opr>ST7</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxrstor</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /mod=11 /reg=1</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fxsave</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /mod=11 /reg=0</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fpxtract</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=34</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fyl2x</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=31</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>fyl2xp1</mnemonic>
+        <class>X87</class>
+        <def>
+            <opc>d9 /mod=11 /x87=39</opc>
+        </def>
+    </instruction>
+
+     <instruction>
+        <mnemonic>hlt</mnemonic>
+        <def>
+            <opc>f4</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>idiv</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=7</opc>
+            <opr>Ev</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=7</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>in</mnemonic>
+        <def>
+            <opc>e4</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>e5</opc>
+            <opr>eAX Ib</opr>
+        </def>
+        <def>
+            <opc>ec</opc>
+            <opr>AL DX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>ed</opc>
+            <opr>eAX DX</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>imul</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f af</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=5</opc>
+            <opr>Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=5</opc>
+            <opr>Ev</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>69</opc>
+            <opr>Gv Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>6b</opc>
+            <opr>Gv Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>inc</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>40</opc>
+            <opr>eAX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>41</opc>
+            <opr>eCX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>42</opc>
+            <opr>eDX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>43</opc>
+            <opr>eBX</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>44</opc>
+            <opr>eSP</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>45</opc>
+            <opr>eBP</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>46</opc>
+            <opr>eSI</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>47</opc>
+            <opr>eDI</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=0</opc>
+            <opr>Ev</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>fe /reg=0</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>insb</mnemonic>
+        <def>
+            <opc>6c</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>insw</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>6d /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>insd</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>6d /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>int1</mnemonic>
+        <def>
+            <opc>f1</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>int3</mnemonic>
+        <def>
+            <opc>cc</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>int</mnemonic>
+        <def>
+            <opc>cd</opc>
+            <opr>Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>into</mnemonic>
+        <def>
+            <opc>ce</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>invd</mnemonic>
+        <def>
+            <opc>0f 08</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>invept</mnemonic>
+        <vendor>intel</vendor>
+        <def>
+            <opc>sse66 0f 38 80 /m=32</opc>
+            <opr>Gd Mo</opr>
+        </def>
+        <def>
+            <opc>sse66 0f 38 80 /m=64</opc>
+            <opr>Gq Mo</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>invlpg</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=7 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>invlpga</mnemonic>
+        <vendor>amd</vendor>
+        <def>
+            <opc>0f 01 /reg=3 /mod=11 /rm=7</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>invvpid</mnemonic>
+        <vendor>intel</vendor>
+        <def>
+            <opc>sse66 0f 38 81 /m=32</opc>
+            <opr>Gd Mo</opr>
+        </def>
+        <def>
+            <opc>sse66 0f 38 81 /m=64</opc>
+            <opr>Gq Mo</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>iretw</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>cf /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>iretd</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>cf /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>iretq</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>cf /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jo</mnemonic>
+        <def>
+            <opc>70</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 80</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jno</mnemonic>
+        <def>
+            <opc>71</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 81</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jb</mnemonic>
+        <def>
+            <opc>72</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 82</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jae</mnemonic>
+        <def>
+            <opc>73</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 83</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jz</mnemonic>
+        <def>
+            <opc>74</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 84</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jnz</mnemonic>
+        <def>
+            <opc>75</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 85</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jbe</mnemonic>
+        <def>
+            <opc>76</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 86</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ja</mnemonic>
+        <def>
+            <opc>77</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 87</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>js</mnemonic>
+        <def>
+            <opc>78</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 88</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jns</mnemonic>
+        <def>
+            <opc>79</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 89</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jp</mnemonic>
+        <def>
+            <opc>7a</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8a</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jnp</mnemonic>
+        <def>
+            <opc>7b</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8b</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jl</mnemonic>
+        <def>
+            <opc>7c</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8c</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jge</mnemonic>
+        <def>
+            <opc>7d</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8d</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jle</mnemonic>
+        <def>
+            <opc>7e</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8e</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jg</mnemonic>
+        <def>
+            <opc>7f</opc>
+            <opr>Jb</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>0f 8f</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jcxz</mnemonic>
+        <def>
+            <pfx>aso</pfx>
+            <opc>e3 /a=16</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jecxz</mnemonic>
+        <def>
+            <pfx>aso</pfx>
+            <opc>e3 /a=32</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jrcxz</mnemonic>
+        <def>
+            <pfx>aso</pfx>
+            <opc>e3 /a=64</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>jmp</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=4</opc>
+            <opr>Ev</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=5</opc>
+            <opr>Ep</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>e9</opc>
+            <opr>Jz</opr>
+            <mode>def64 depM</mode>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <opc>ea</opc>
+            <opr>Ap</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>eb</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lahf</mnemonic>
+        <def>
+            <opc>9f</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lar</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 02</opc>
+            <opr>Gv Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lddqu</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f f0</opc>
+            <opr>V M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ldmxcsr</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /reg=2 /mod=11</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lds</mnemonic>
+        <def>
+            <pfx>aso oso</pfx>
+            <opc>c5</opc>
+            <opr>Gv M</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lea</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>8d</opc>
+            <opr>Gv M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>les</mnemonic>
+        <def>
+            <pfx>aso oso</pfx>
+            <opc>c4</opc>
+            <opr>Gv M</opr>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lfs</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b4</opc>
+            <opr>Gz M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lgs</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b5</opc>
+            <opr>Gz M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lidt</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=3 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lss</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b2</opc>
+            <opr>Gz M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>leave</mnemonic>
+        <def>
+            <opc>c9</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lfence</mnemonic>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=0</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=1</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=2</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=3</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=4</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=5</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=6</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=5 /mod=11 /rm=7</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lgdt</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=2 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lldt</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=2</opc>
+            <opr>Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lmsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=6 /mod=!11</opc>
+            <opr>Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lock</mnemonic>
+        <def>
+            <opc>f0</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lodsb</mnemonic>
+        <def>
+            <pfx>seg</pfx>
+            <opc>ac</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lodsw</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ad /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lodsd</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ad /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lodsq</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ad /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>loopnz</mnemonic>
+        <def>
+            <opc>e0</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>loope</mnemonic>
+        <def>
+            <opc>e1</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>loop</mnemonic>
+        <def>
+            <opc>e2</opc>
+            <opr>Jb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>lsl</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f 03</opc>
+            <opr>Gv Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ltr</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=3</opc>
+            <opr>Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>maskmovq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f7</opc>
+            <opr>P PR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>maxpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>maxps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>maxsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 5f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>maxss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5f</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mfence</mnemonic>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=0</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=1</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=2</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=3</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=4</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=5</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=6</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=6 /mod=11 /rm=7</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>minpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5d</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>minps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5d</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>minsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 5d</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>minss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5d</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>monitor</mnemonic>
+        <def>
+            <opc>0f 01 /reg=1 /mod=11 /rm=0</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>montmul</mnemonic>
+        <def>
+            <opc>0f a6 /mod=11 /rm=0 /reg=0</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mov</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c6 /reg=0</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c7 /reg=0</opc>
+            <opr>Ev Iz</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>88</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>89</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>8a</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>8b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexr rexx rexb</pfx>
+            <opc>8c</opc>
+            <opr>Ev S</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexr rexx rexb</pfx>
+            <opc>8e</opc>
+            <opr>S Ev</opr>
+        </def>
+        <def>
+            <opc>a0</opc>
+            <opr>AL Ob</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw</pfx>
+            <opc>a1</opc>
+            <opr>rAX Ov</opr>
+        </def>
+        <def>
+            <opc>a2</opc>
+            <opr>Ob AL</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw</pfx>
+            <opc>a3</opc>
+            <opr>Ov rAX</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b0</opc>
+            <opr>ALr8b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b1</opc>
+            <opr>CLr9b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b2</opc>
+            <opr>DLr10b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b3</opc>
+            <opr>BLr11b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b4</opc>
+            <opr>AHr12b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b5</opc>
+            <opr>CHr13b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b6</opc>
+            <opr>DHr14b Ib</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>b7</opc>
+            <opr>BHr15b Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>b8</opc>
+            <opr>rAXr8 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>b9</opc>
+            <opr>rCXr9 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>ba</opc>
+            <opr>rDXr10 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>bb</opc>
+            <opr>rBXr11 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>bc</opc>
+            <opr>rSPr12 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>bd</opc>
+            <opr>rBPr13 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>be</opc>
+            <opr>rSIr14 Iv</opr>
+        </def>
+        <def>
+            <pfx>oso rexw rexb</pfx>
+            <opc>bf</opc>
+            <opr>rDIr15 Iv</opr>
+        </def>
+        <def>
+            <pfx>rexr</pfx>
+            <opc>0f 20</opc>
+            <opr>R C</opr>
+        </def>
+        <def>
+            <pfx>rexr</pfx>
+            <opc>0f 21</opc>
+            <opr>R D</opr>
+        </def>
+        <def>
+            <pfx>rexr</pfx>
+            <opc>0f 22</opc>
+            <opr>C R</opr>
+        </def>
+        <def>
+            <pfx>rexr</pfx>
+            <opc>0f 23</opc>
+            <opr>D R</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movapd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 28</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 29</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movaps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 28</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 29</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movd</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>sse66 0f 6e</opc>
+            <opr>V Ex</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 6e</opc>
+            <opr>P Ex</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>sse66 0f 7e</opc>
+            <opr>Ex V</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 7e</opc>
+            <opr>Ex P</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movhpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 16 /mod=!11</opc>
+            <opr>V M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 17</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movhps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 16 /mod=!11</opc>
+            <opr>V M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 17</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movlhps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 16 /mod=11</opc>
+            <opr>V VR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movlpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 12 /mod=!11</opc>
+            <opr>V M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 13</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movlps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 12 /mod=!11</opc>
+            <opr>V M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 13</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movhlps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 12 /mod=11</opc>
+            <opr>V VR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movmskpd</mnemonic>
+        <def>
+            <pfx>oso rexr rexb</pfx>
+            <opc>sse66 0f 50</opc>
+            <opr>Gd VR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movmskps</mnemonic>
+        <def>
+            <pfx>oso rexr rexb</pfx>
+            <opc>0f 50</opc>
+            <opr>Gd VR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movntdq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e7</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movnti</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f c3</opc>
+            <opr>M Gy</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movntpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2b</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movntps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2b</opc>
+            <opr>M V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movntq</mnemonic>
+        <def>
+            <opc>0f e7</opc>
+            <opr>M P</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 6f</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d6</opc>
+            <opr>W V</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 7e</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 7f</opc>
+            <opr>Q P</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsb</mnemonic>
+        <def>
+            <pfx>seg</pfx>
+            <opc>a4</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsw</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>a5 /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsd</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>a5 /o=32</opc>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 10</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 11</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsq</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>a5 /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 10</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 11</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movsx</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f be</opc>
+            <opr>Gv Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f bf</opc>
+            <opr>Gv Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movupd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 10</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 11</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movups</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 10</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 11</opc>
+            <opr>W V</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>movzx</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b6</opc>
+            <opr>Gv Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f b7</opc>
+            <opr>Gv Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mul</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=4</opc>
+            <opr>Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=4</opc>
+            <opr>Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mulpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 59</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mulps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 59</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mulsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 59</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mulss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 59</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>mwait</mnemonic>
+        <def>
+            <opc>0f 01 /reg=1 /mod=11 /rm=1</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>neg</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=3</opc>
+            <opr>Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=3</opc>
+            <opr>Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>nop</mnemonic>
+        <def>
+            <opc>90</opc>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 19</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1a</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1b</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1c</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1d</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1e</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 1f</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>not</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=2</opc>
+            <opr>Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=2</opc>
+            <opr>Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>or</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>08</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>09</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0a</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>0c</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>0d</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=1</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=1</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=1</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=1</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>orpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 56</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>orps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 56</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>out</mnemonic>
+        <def>
+            <opc>e6</opc>
+            <opr>Ib AL</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>e7</opc>
+            <opr>Ib eAX</opr>
+        </def>
+        <def>
+            <opc>ee</opc>
+            <opr>DX AL</opr>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>ef</opc>
+            <opr>DX eAX</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>outsb</mnemonic>
+        <def>
+            <opc>6e</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>outsw</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>6f /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>outsd</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>6f /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>outsq</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>6f /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>packsswb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 63</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 63</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>packssdw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 6b</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 6b</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>packuswb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 67</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 67</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f fc</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f fc</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f fd</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f fd</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f fe</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f fe</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+
+    <instruction>
+        <mnemonic>paddsb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f ec</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f ec</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f ed</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f ed</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddusb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f dc</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f dc</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>paddusw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f dd</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f dd</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pand</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f db</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f db</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pandn</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f df</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f df</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pavgb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e0</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e0</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pavgw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e3</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e3</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpeqb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 74</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 74</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpeqw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 75</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 75</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpeqd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 76</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 76</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpgtb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 64</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 64</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpgtw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 65</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 65</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pcmpgtd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 66</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 66</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pextrb</mnemonic>
+        <def>
+            <pfx>aso rexr rexb</pfx>
+            <opc>sse66 0f 3a 14</opc>
+            <opr>MbRv V Ib</opr>
+            <mode>def64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pextrd</mnemonic>
+        <def>
+            <pfx>aso rexr rexw rexb</pfx>
+            <opc>sse66 0f 3a 16 /o=16</opc>
+            <opr>Ev V Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexw rexb</pfx>
+            <opc>sse66 0f 3a 16 /o=32</opc>
+            <opr>Ev V Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pextrq</mnemonic>
+        <def>
+            <pfx>aso rexr rexw rexb</pfx>
+            <opc>sse66 0f 3a 16 /o=64</opc>
+            <opr>Ev V Ib</opr>
+            <mode>def64</mode>
+        </def>
+    </instruction>
+
+   <instruction>
+        <mnemonic>pextrw</mnemonic>
+        <def>
+            <pfx>aso rexr rexb</pfx>
+            <opc>sse66 0f c5</opc>
+            <opr>Gd VR Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f c5</opc>
+            <opr>Gd PR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pinsrw</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f c4</opc>
+            <opr>P Ew Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>sse66 0f c4</opc>
+            <opr>V Ew Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmaddwd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f5</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f5</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmaxsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f ee</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f ee</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmaxub</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f de</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f de</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pminsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f ea</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f ea</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pminub</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f da</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f da</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmovmskb</mnemonic>
+        <def>
+            <pfx>rexr rexb</pfx>
+            <opc>sse66 0f d7</opc>
+            <opr>Gd VR</opr>
+        </def>
+        <def>
+            <pfx>oso rexr rexb</pfx>
+            <opc>0f d7</opc>
+            <opr>Gd PR</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmulhuw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e4</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e4</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmulhw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e5</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e5</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmullw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d5</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d5</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pop</mnemonic>
+        <def>
+            <opc>07</opc>
+            <opr>ES</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>17</opc>
+            <opr>SS</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>1f</opc>
+            <opr>DS</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>0f a9</opc>
+            <opr>GS</opr>
+        </def>
+        <def>
+            <opc>0f a1</opc>
+            <opr>FS</opr>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>58</opc>
+            <opr>rAXr8</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>59</opc>
+            <opr>rCXr9</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5a</opc>
+            <opr>rDXr10</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5b</opc>
+            <opr>rBXr11</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5c</opc>
+            <opr>rSPr12</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5d</opc>
+            <opr>rBPr13</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5e</opc>
+            <opr>rSIr14</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>5f</opc>
+            <opr>rDIr15</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>8f /reg=0</opc>
+            <opr>Ev</opr>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>popa</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>61 /o=16</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>popad</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>61 /o=32</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>popfw</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9d /m=32 /o=16</opc>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9d /m=16 /o=16</opc>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>popfd</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9d /m=16 /o=32</opc>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9d /m=32 /o=32</opc>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>popfq</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9d /m=64 /o=64</opc>
+            <mode>def64 depM</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>por</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f eb</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f eb</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>prefetch</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=0</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=1</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=2</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=3</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=4</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=5</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=6</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 0d /reg=7</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>prefetchnta</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 18 /reg=0</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>prefetcht0</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 18 /reg=1</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>prefetcht1</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 18 /reg=2</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>prefetcht2</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f 18 /reg=3</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psadbw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f6</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f6</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pshufw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 70</opc>
+            <opr>P Q Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psllw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f1</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f1</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 71 /reg=6</opc>
+            <opr>VR Ib</opr>
+        </def>
+        <def>
+            <opc>0f 71 /reg=6</opc>
+            <opr>PR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pslld</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f2</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f2</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 72 /reg=6</opc>
+            <opr>VR Ib</opr>
+        </def>
+        <def>
+            <opc>0f 72 /reg=6</opc>
+            <opr>PR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psllq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f3</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f3</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 73 /reg=6</opc>
+            <opr>VR Ib</opr>
+        </def>
+        <def>
+            <opc>0f 73 /reg=6</opc>
+            <opr>PR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psraw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e1</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e1</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 71 /reg=4</opc>
+            <opr>VR Ib</opr>
+        </def>
+        <def>
+            <opc>0f 71 /reg=4</opc>
+            <opr>PR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psrad</mnemonic>
+        <def>
+            <opc>0f 72 /reg=4</opc>
+            <opr>PR Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e2</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e2</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 72 /reg=4</opc>
+            <opr>VR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psrlw</mnemonic>
+        <def>
+            <opc>0f 71 /reg=2</opc>
+            <opr>PR Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d1</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d1</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 71 /reg=2</opc>
+            <opr>VR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psrld</mnemonic>
+        <def>
+            <opc>0f 72 /reg=2</opc>
+            <opr>PR Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d2</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d2</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 72 /reg=2</opc>
+            <opr>VR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psrlq</mnemonic>
+        <def>
+            <opc>0f 73 /reg=2</opc>
+            <opr>PR Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d3</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d3</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>rexb</pfx>
+            <opc>sse66 0f 73 /reg=2</opc>
+            <opr>VR Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f8</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f8</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f f9</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f f9</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f fa</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f fa</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubsb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e8</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e8</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f e9</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f e9</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubusb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d8</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d8</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>psubusw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f d9</opc>
+            <opr>P Q</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f d9</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpckhbw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 68</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 68</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpckhwd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 69</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 69</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpckhdq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 6a</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 6a</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpcklbw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 60</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 60</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpcklwd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 61</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 61</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>punpckldq</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 62</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 62</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pi2fw</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=0c</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pi2fd</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=0d</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pf2iw</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=1c</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pf2id</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=1d</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfnacc</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=8a</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfpnacc</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=8e</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfcmpge</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=90</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfmin</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=94</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfrcp</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=96</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfrsqrt</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=97</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfsub</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=9a</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfadd</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=9e</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfcmpgt</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=a0</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfmax</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=a4</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfrcpit1</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=a6</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfrsqit1</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=a7</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfsubr</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=aa</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfacc</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=ae</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfcmpeq</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=b0</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfmul</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=b4</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pfrcpit2</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=b6</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pmulhrw</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=b7</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pswapd</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=bb</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pavgusb</mnemonic>
+        <def>
+            <opc>0f 0f /3dnow=bf</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>push</mnemonic>
+        <def>
+            <opc>06</opc>
+            <opr>ES</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>0e</opc>
+            <opr>CS</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>16</opc>
+            <opr>SS</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>1e</opc>
+            <opr>DS</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <opc>0f a8</opc>
+            <opr>GS</opr>
+        </def>
+        <def>
+            <opc>0f a0</opc>
+            <opr>FS</opr>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>50</opc>
+            <opr>rAXr8</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>51</opc>
+            <opr>rCXr9</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>52</opc>
+            <opr>rDXr10</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>53</opc>
+            <opr>rBXr11</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>54</opc>
+            <opr>rSPr12</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>55</opc>
+            <opr>rBPr13</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>56</opc>
+            <opr>rSIr14</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso rexb</pfx>
+            <opc>57</opc>
+            <opr>rDIr15</opr>
+            <mode>def64 depM</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>68</opc>
+            <opr>Iz</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>ff /reg=6</opc>
+            <opr>Ev</opr>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <opc>6a</opc>
+            <opr>Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pusha</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>60 /o=16</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pushad</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>60 /o=32</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pushfw</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9c /m=32 /o=16</opc>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9c /m=16 /o=16</opc>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>9c /m=64 /o=16</opc>
+            <mode>def64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pushfd</mnemonic>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9c /m=16 /o=32</opc>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>oso</pfx>
+            <opc>9c /m=32 /o=32</opc>
+            <mode>def64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pushfq</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>9c /m=64 /o=32</opc>
+            <mode>def64</mode>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>9c /m=64 /o=64</opc>
+            <mode>def64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>pxor</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f ef</opc>
+            <opr>V W</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f ef</opc>
+            <opr>P Q</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rcl</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=2</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=2</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=2</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=2</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=2</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=2</opc>
+            <opr>Ev I1</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rcr</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=3</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=3</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=3</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=3</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=3</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=3</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rol</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=0</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=0</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=0</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=0</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn> 
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=0</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn> 
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=0</opc>
+            <opr>Ev Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ror</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=1</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=1</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=1</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=1</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=1</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=1</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rcpps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 53</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rcpss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 53</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rdmsr</mnemonic>
+        <def>
+            <opc>0f 32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rdpmc</mnemonic>
+        <def>
+            <opc>0f 33</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rdtsc</mnemonic>
+        <def>
+            <opc>0f 31</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rdtscp</mnemonic>
+        <vendor>amd</vendor>
+        <def>
+            <opc>0f 01 /reg=7 /mod=11 /rm=1</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>repne</mnemonic>
+        <def>
+            <opc>f2</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rep</mnemonic>
+        <def>
+            <opc>f3</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ret</mnemonic>
+        <def>
+            <opc>c2</opc>
+            <opr>Iw</opr>
+        </def>
+        <def>
+            <opc>c3</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>retf</mnemonic>
+        <def>
+            <opc>ca</opc>
+            <opr>Iw</opr>
+        </def>
+        <def>
+            <opc>cb</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rsm</mnemonic>
+        <def>
+            <opc>0f aa</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rsqrtps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 52</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>rsqrtss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 52</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sahf</mnemonic>
+        <def>
+            <opc>9e</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sal</mnemonic>
+    </instruction>
+
+    <instruction>
+        <mnemonic>salc</mnemonic>
+        <def>
+            <opc>d6</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sar</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=7</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=7</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=7</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=7</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=7</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=7</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shl</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=6</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=6</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=6</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=6</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=6</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=4</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>d2 /reg=4</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=4</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=4</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=4</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=4</opc>
+            <opr>Ev CL</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=6</opc>
+            <opr>Ev I1</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shr</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>c1 /reg=5</opc>
+            <opr>Ev Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d2 /reg=5</opc>
+            <opr>Eb CL</opr>
+            <syn>cast</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d1 /reg=5</opc>
+            <opr>Ev I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>d0 /reg=5</opc>
+            <opr>Eb I1</opr>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>c0 /reg=5</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>d3 /reg=5</opc>
+            <opr>Ev CL</opr>
+            <syn>cast</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sbb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>18</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>19</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>1a</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>1b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>1c</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>1d</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=3</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=3</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=3</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=3</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>scasb</mnemonic>
+        <def>
+            <opc>ae</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>scasw</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>af /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>scasd</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>af /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>scasq</mnemonic>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>af /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>seto</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 90</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setno</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 91</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 92</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setnb</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 93</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setz</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 94</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setnz</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 95</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setbe</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 96</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>seta</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 97</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sets</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 98</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setns</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 99</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setp</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9a</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setnp</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9b</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setl</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9c</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setge</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9d</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setle</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9e</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>setg</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 9f</opc>
+            <opr>Eb</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sfence</mnemonic>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=0</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=1</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=2</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=3</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=4</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=5</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=6</opc>
+        </def>
+        <def>
+            <opc>0f ae /reg=7 /mod=11 /rm=7</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sgdt</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=0 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shld</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f a4</opc>
+            <opr>Ev Gv Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f a5</opc>
+            <opr>Ev Gv CL</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shrd</mnemonic>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ac</opc>
+            <opr>Ev Gv Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>0f ad</opc>
+            <opr>Ev Gv CL</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shufpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f c6</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>shufps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f c6</opc>
+            <opr>V W Ib</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sidt</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=1 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sldt</mnemonic>
+        <def>
+            <pfx>aso oso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=0</opc>
+            <opr>MwRv</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>smsw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 01 /reg=4 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sqrtps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 51</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sqrtpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 51</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sqrtsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 51</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sqrtss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 51</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stc</mnemonic>
+        <def>
+            <opc>f9</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>std</mnemonic>
+        <def>
+            <opc>fd</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stgi</mnemonic>
+        <vendor>amd</vendor>
+        <def>
+            <opc>0f 01 /reg=3 /mod=11 /rm=4</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sti</mnemonic>
+        <def>
+            <opc>fb</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>skinit</mnemonic>
+        <vendor>amd</vendor>
+        <def>
+            <opc>0f 01 /reg=3 /mod=11 /rm=6</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stmxcsr</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /mod=11 /reg=3</opc>
+            <opr>Md</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stosb</mnemonic>
+        <def>
+            <pfx>seg</pfx>
+            <opc>aa</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stosw</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ab /o=16</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stosd</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ab /o=32</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>stosq</mnemonic>
+        <def>
+            <pfx>seg oso rexw</pfx>
+            <opc>ab /o=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>str</mnemonic>
+        <def>
+            <pfx>aso oso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=1</opc>
+            <opr>Ev</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sub</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>28</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>29</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>2a</opc>
+            <opr>Gb Eb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>2b</opc>
+            <opr>Gv Ev</opr>
+        </def>
+        <def>
+            <opc>2c</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>2d</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>80 /reg=5</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>81 /reg=5</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>82 /reg=5</opc>
+            <opr>Eb Ib</opr>
+            <mode>inv64</mode>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>83 /reg=5</opc>
+            <opr>Ev Ib</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>subpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 5c</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>subps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 5c</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>subsd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef2 0f 5c</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>subss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>ssef3 0f 5c</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>swapgs</mnemonic>
+        <def>
+            <opc>0f 01 /reg=7 /mod=11 /rm=0</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>syscall</mnemonic>
+        <def>
+            <opc>0f 05</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sysenter</mnemonic>
+        <def>
+            <opc>0f 34</opc>
+            <mode>inv64</mode>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sysexit</mnemonic>
+        <def>
+            <opc>0f 35</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>sysret</mnemonic>
+        <def>
+            <opc>0f 07</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>test</mnemonic>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=0</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>84</opc>
+            <opr>Eb Gb</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>85</opc>
+            <opr>Ev Gv</opr>
+        </def>
+        <def>
+            <opc>a8</opc>
+            <opr>AL Ib</opr>
+        </def>
+        <def>
+            <pfx>oso rexw</pfx>
+            <opc>a9</opc>
+            <opr>rAX Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>f6 /reg=1</opc>
+            <opr>Eb Ib</opr>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=0</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+        <def>
+            <pfx>aso oso rexw rexr rexx rexb</pfx>
+            <opc>f7 /reg=1</opc>
+            <opr>Ev Iz</opr>
+            <syn>sext</syn>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ucomisd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 2e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ucomiss</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 2e</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>ud2</mnemonic>
+        <def>
+            <opc>0f 0b</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>unpckhpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 15</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>unpckhps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 15</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>unpcklps</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 14</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>unpcklpd</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>sse66 0f 14</opc>
+            <opr>V W</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>verr</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=4</opc>
+            <opr>Ew</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>verw</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f 00 /reg=5</opc&g