[DFG][MIPS] Simplify DFG code by increasing MIPS temporary registers
authorutatane.tea@gmail.com <utatane.tea@gmail.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Tue, 8 May 2018 01:13:03 +0000 (01:13 +0000)
committerutatane.tea@gmail.com <utatane.tea@gmail.com@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Tue, 8 May 2018 01:13:03 +0000 (01:13 +0000)
commitc8d60ee7998bdbfe96b1ae59fee220710b46cbf0
tree430c3ab0195d0be31f50c53b85ebd30efbef81ef
parente94fa6f4beec700107c72e804b3c6794fddce32e
[DFG][MIPS] Simplify DFG code by increasing MIPS temporary registers
https://bugs.webkit.org/show_bug.cgi?id=185371

Reviewed by Mark Lam.

Since MIPS GPRInfo claims it has only 7 registers, some of DFG code exhausts registers.
As a result, we need to maintain separated code for MIPS. This increases DFG maintenance burden,
but actually MIPS have much more registers.

This patch adds $a0 - $a3 to temporary registers. This is OK since our temporary registers can be overlapped with
argument registers (see ARM, X86 implementations). These registers are caller-save ones, so we do not need to
have extra mechanism.

Then, we remove several unnecessary MIPS code in our JIT infrastructure.

* dfg/DFGByteCodeParser.cpp:
(JSC::DFG::ByteCodeParser::handleIntrinsicCall):
* dfg/DFGFixupPhase.cpp:
(JSC::DFG::FixupPhase::fixupNode):
* dfg/DFGSpeculativeJIT32_64.cpp:
(JSC::DFG::SpeculativeJIT::compile):
* jit/CCallHelpers.h:
* jit/GPRInfo.h:
(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::toIndex):
* offlineasm/mips.rb:

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@231472 268f45cc-cd09-0410-ab3c-d52691b4dbfc
Source/JavaScriptCore/ChangeLog
Source/JavaScriptCore/dfg/DFGByteCodeParser.cpp
Source/JavaScriptCore/dfg/DFGFixupPhase.cpp
Source/JavaScriptCore/dfg/DFGSpeculativeJIT32_64.cpp
Source/JavaScriptCore/jit/CCallHelpers.h
Source/JavaScriptCore/jit/GPRInfo.h
Source/JavaScriptCore/offlineasm/mips.rb