Refactoring the fpu code generator for the ARM port
authorzherczeg@webkit.org <zherczeg@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Fri, 13 Aug 2010 06:49:16 +0000 (06:49 +0000)
committerzherczeg@webkit.org <zherczeg@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Fri, 13 Aug 2010 06:49:16 +0000 (06:49 +0000)
commitba7438c3e9e2b2623c280afb4dc2c06b497dcb5d
tree4fc92f68ac5452b28de1e73f3f7099882024bb05
parentc5261419e0cf1dd943660e112ee4fe716c84af39
Refactoring the fpu code generator for the ARM port
https://bugs.webkit.org/show_bug.cgi?id=43842

Reviewed by Gavin Barraclough.

Support up to 32 double precision registers, and the
recent VFP instruction formats. This patch is mainly
a style change which keeps the current functionality.

* assembler/ARMAssembler.h:
(JSC::ARMRegisters::):
(JSC::ARMAssembler::):
(JSC::ARMAssembler::emitInst):
(JSC::ARMAssembler::emitDoublePrecisionInst):
(JSC::ARMAssembler::emitSinglePrecisionInst):
(JSC::ARMAssembler::vadd_f64_r):
(JSC::ARMAssembler::vdiv_f64_r):
(JSC::ARMAssembler::vsub_f64_r):
(JSC::ARMAssembler::vmul_f64_r):
(JSC::ARMAssembler::vcmp_f64_r):
(JSC::ARMAssembler::vsqrt_f64_r):
(JSC::ARMAssembler::vmov_vfp_r):
(JSC::ARMAssembler::vmov_arm_r):
(JSC::ARMAssembler::vcvt_f64_s32_r):
(JSC::ARMAssembler::vcvt_s32_f64_r):
(JSC::ARMAssembler::vmrs_apsr):
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::sqrtDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::branchDouble):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):

git-svn-id: https://svn.webkit.org/repository/webkit/trunk@65303 268f45cc-cd09-0410-ab3c-d52691b4dbfc
JavaScriptCore/ChangeLog
JavaScriptCore/assembler/ARMAssembler.h
JavaScriptCore/assembler/MacroAssemblerARM.h